As more and more custom/analog designs migrate to advanced process nodes (<65nm), design teams are being confronted with an ever-increasing need to better manage the impact of parasitics throughout the entire custom/analog design flow. In addition, more and more layout design teams are finding themselves drawn into the front-end design team's simulation flow and their path to parasitic closure.
But why is a new approach needed, when many custom/analog methodologies today already incorporate estimated layout dependent effects in PCell device models, device callbacks, and in estimated wire models? At advanced process nodes, layout-dependent effects increasingly not only have to take into account separate device and wire effects, but also the effects of devices and wires related to their surrounding environments,. Anywhere from 20-30% of a circuit's performance can be attributed to the effects of the surrounding environment.
Two such layout dependent effects are shallow trench isolation (STI) and well proximity effect (WPE). STI effects for a device must take into account the distance of a gate to each edge of the diffusion, gate to gate separation, and the overall length of the diffusion. As such, any handcrafting of devices or groups of devices -- including any folding, merging, abutting, and dummy insertion -- all impact STI effects and a consequently a device's performance.
Figure 1 -- STI Illustration
WPE effects must take into account the distance or proximity of a device to the edge of the well, and in turn a device's performance is directly correlated to this distance. This effect can only be accurately determined after placement and any handcrafting, including any merging of multiple devices into common wells.
Continuing with inaccurate parasitic estimation methodologies or inserting time-consuming handcrafted layouts in the midst of highly iterative front-end simulation flows would not only have a negative impact on the productivity of both the front-end design team and layout team, but would increase overall risk in the success of a product.
Thus, new custom/analog design flow methodologies that provide more accurate parasitic estimates faster and sooner in the design flow are needed for advanced node designs.
The Virtuoso parasitic-aware design flow provides parasitic closure faster and in fewer design iterations, without sacrificing design performance on advanced node designs. The Virtuoso parasitic-aware design flow spans the design, verification and implementation phases of custom/analog design. For an overview of the entire Virtuoso parasitic-aware design flow, please see Richard Goering's blog, and for details on the design and verification phases, please see Rama Jupalli's blog. The remainder of this blog will focus on the physical implementation or layout phase, and specifically how Rapid Analog Prototyping delivers more accurate parasitic estimates faster.
Better Productivity for Managing Parasitics
Rapid Analog Prototyping brings handcrafted layout a needed boost in productivity required for managing parasitics in advanced node designs. It does this by selectively automating key aspects of custom/analog layout, providing direct access to advanced automated technologies from the familiar industry-standard Virtuoso layout cockpit, all integrated on a common Open Access database.
By allowing layout designers to selectively automate key aspects of custom/analog layout, they can rapidly create layout prototypes with more accurate parasitics for front-end designers, while focusing their creativity on precision hand crafting final layouts.
There are three key Rapid Analog Prototyping tasks in the physical implementation or layout phase of the Virtuoso parasitic-aware design flow:
Virtuoso's advanced module generators are built on SKILL PCells to automatically assist a layout designer in generating complex, highly matched, structured arrays of devices for common analog subcircuits like differential pairs, current mirrors, and more. A layout designer can selectively automate merging, abutting, and interdigitating multiple devices, as well as inserting dummies and guardrings. The module generators rapidly create DRC and LVS correct layout ready for parasitic extraction while accurately reflecting layout dependent effects such as STI effects.
Virtuoso's advanced custom/analog device placement is capable of rapid constraint driven placement of SKILL PCells and module generators. A layout designer can selectively create rapid placement prototypes in three increasing modes of automation: quick placement for quick area estimation, quick placement based on device positioning in the schematic, and fully automated placement that minimizes area and overall wire length and automatically places similar devices in clusters and merges common wells. The rapid analog placements are DRC and LVS correct layouts ready for parasitic extraction, while accurately reflecting layout dependent effects such as WPE effects.
Virtuoso's advanced custom/analog net routing is provided by the Space-Based Router technology. A layout designer can selectively complete net routing in increasing modes of automation - interactive wire editing, assisted autorouting and fully automated routing. All net routing is DRC and LVS correct layout ready for parasitic extraction, while more accurately reflecting layout dependent effects of wires.
Rapid Analog Prototyping and the Virtuoso parasitic-aware design flow are part of a recently announced Cadence Silicon Realization custom/analog flow focused on unified intent, abstraction, and convergence. This flow leverages the breadth, depth, and integration of Virtuoso Schematic Editor, Virtuoso Analog Design Environment, Virtuoso MMSIM, Virtuoso Layout Suite, and in-design manufacturing Virtuoso DFM.
Please send me your comments on what issues you see with parasitics, how you manage those today in your design flows, and what improvements you would like to see.
Loking forward to see a full demo at DAC in San Diego. After that I can write my comments...