If your only news source were some of the common EDA pundits, you would likely believe that VoltageStorm is all but dead, and that Apache was the only game in town, but that is very far from the truth. So what has happened to VoltageStorm since Cadence acquired Simplex back in 2003? The easy answer is “a lot”.
If you have read my bio, I came to Cadence from Simplex and so power integrity analysis is close to my heart, and at the time of the acquisition, VoltageStorm PE was the recognized standard for static power integrity analysis, and Apache had taken the lead in the dynamic power rail analysis space (and I definitely wasn’t a happy camper because of this).
The whole VoltageStorm team determined that there needed to be a very focused effort to develop a dynamic VoltageStorm solution, which resulted in the launch of the VoltageStorm Dynamic Gate Option (VoltageStorm DG) in mid-2005. The new dynamic functionality enabled VoltageStorm to regain market share in the dynamic analysis segment, and with a very solid reputation and a large installed base, VoltageStorm became, and continues to remain, the #1 selling analysis product in the Cadence portfolio.
But we didn’t stop there. As an ex-design engineer, I fully understood the value of power and power rail analysis within the design implementation flow, where analysis results could help create more robust designs prior to signoff analysis, and so we integrated some of the VoltageStorm functionality into the Encounter platform. Today, instead of being used solely for signoff analysis, it is great to see that functionality from VoltageStorm is a critical component within our digital implementation solution.
Encounter Power System … The Next Generation of Power Integrity Analysis
I’m not sure if you caught the announcement, but we recently launched the new Encounter Power System (EPS) at the end of 2008. EPS continues to build on the VoltageStorm engines, but is tightly integrated with the Encounter Timing System (ETS) … the EPS/ETS combination enables an easy-to-use, comprehensive timing-SI-power signoff analysis solution required for advanced designs.
So, plagiarizing the immortal words of Mark Twain, I am very pleased to report that any rumors of VoltageStorm’s death have been greatly exaggerated. On the contrary, VoltageStorm’s functionality is stronger than ever and lives on within the new Encounter Power System products.
By the way, if you haven’t yet learned about ETS and EPS, I encourage you to follow this link to get more information … set your mouse on the “Signoff analysis” tab on the left.
I am very proud of the fact that not only has VoltageStorm survived against tough competition, but the VoltageStorm functionality lives on as an integral part of the Encounter Digital Implementation System and as a next generation signoff analysis product.
I plan to start off some more threads on power and power integrity analysis, so if you have comments or questions around power integrity analysis, watch this space. If there is something specific you would like to know, let me know and I will get you the answers.
Thanks for the update.
I am looking for something that can be used by RF layout designers to aid while building the power routes. This will help in analyzing the nets after the routes are complete. It would be good to have some capability to find some of this information while the power routes are under development, does "Virtuoso Analog VoltageStorm" have this type of ability.
Richard, I assume that you are using Virtuoso to implement your analog/RF designs, in which case I have good news for you. We have a couple of simulation-driven solutions that will likely help you ... the Virtuoso Analog VoltageStorm Option (we refer to it as VAVO) enables power integrity (IR Drop, EM) analysis tightly integrated within Virtuoso, while UltraSim offers a standalone EMIR solution for custom/analog designs.
Both solutions will calculate and report IR drop and current flow based on extracted resistance of the power routes, including all parallel paths to multiple power pads.
The VAVO solution enables the creation of a power model that can be used within SoC designs, enabling full-chip analysis of designs that contain digital, analog, RF, memories etc.
Please contact your Cadence account team to get more information.
Power analysis is also something that analog and RF designers find useful. When are these features going to be available for something other than digital platforms. We have been told that voltage storm is not recommend for our needs right now.
One feature that would be great is a way to capture metal resistances (Including some way to assign resistance between common pads.) between two given points in a layout.
This is a great question, let me try to answer it.
The accuracy of Early Rail Analysis (ERA) is directly related to the accuracy of input data that is used to drive the analysis. If all input conditions were the same, then ERA would give results that are very similar to signoff because it is using the same analysis engines.
Why only similar? Because the ERA has been designed to be very fast, we have made some approximations that slightly impact accuracy, but not in a huge way.
The value of ERA is to enable you to very rapidly assess whether your proposed power rail structures are robust at an early stage in the design. The goal is to optimize the power network early, then tune them further when additional (more accurate and more comprehensive) design data is available. Following this approach will help you avoid having to make difficult-to-implement, radical changes later in your flow.
It is very important to first check the power rails using static analysis, which helps you make sure that your power rail network doesn't have too much IR drop due to resistive routing. Once your power network is robust from a resistive view, you can then tune it with de-coupling capacitors to help counter dynamic IR drop caused by simultaneous switching.
Experience from working with many customers shows that you should always analyze and optimize for resistance-based IR drop before you try to tune the de-caps. Adding de-caps may not significantly impact IR drop caused by resistance, which is better addressed by directly modifying the power routes.
Hope this helps you :)
Thanks for your post. I find that Early Rail Analysis feature of SoC Encounter is pretty useful. However, when I tried it I got IRdrop results that differ pretty much from sign-off results. Could please provide more information about the usage of this feature in order to be able to estimate IRdrop in the early design stage? Thanks!