I'm looking forward to heading out to San Francisco next week for the 46th Design Automation Conference. For my money, it's hard to beat San Francisco as a location for a trade show. Cable cars, Fisherman's Wharf, Alcatraz, San Francisco Giants baseball, Napa/Sonoma Wine Country...what a great part of the country. And DAC itself is a great time in my experience. You get to learn about all the latest things EDA companies are offering, what other chip design companies are working on, and best of all you get to catch up with old friends that you haven't seen in a while.
For my part in the conference, I'll be presenting a demonstration of a new capability we've been working on that bridges the gap between chip estimation and chip implementation. We'll show how the Cadence InCyte Chip Estimator can interface with the Encounter Digital Implementation System to establish a formal and quantified exchange of design data between chip architects and chip implementation leads. This exchange reduces risk by enabling clear communication of design intent and allows each participant in the process to manipulate the design with a level of fidelity appropriate to their role in the project.
Here is an image of the same design with the InCyte Chip Estimator (on the left) and within the Encounter Digital Implementation System (on the right). Each participant works with the design in an environment that has the appropriate level of control and automation for what they need to do, and meaningful design intent exchange occurs as the design is refined:
If you're interesting in learning more about this solution:
For a complete listing of what Cadence has planned for DAC, visit the Cadence DAC mini-site.
I'll be blogging and posting videos/photos of interesting things during the week. If you're planning on attending DAC and would like to say "hi", drop me a message in the Cadence.com Community -or- follow me on Twitter and send me a message. I'd love to meet you.
Question of the Day: Are you planning on attending DAC this year?