Hi Abhishek, Thanks for the comments. I'm not sure what you mean by a complete path in your second item. For the first one, yes - EDI will not anticipate how the logic may get changed, so you'll have to include that celltype if you want it to be part of your selective blockage flow. I encourage you to file an enhancement request if you feel strongly about this behavior.
1. during prects it simplify netlist is set to true then it donot add the new cell in the selective Blockage list.
For eg. if there is OR and AND cell in series... then the tool may replace it to AO cell. but this AO cell doesnot sit in the blockage area. (creating problem in my case)
this problem need to be solved.
2. there should be option that the complete path can be set in the selective blockage
Power grid via stack arrays cause a lot of vertical signal routing congestion.
You will improve routability if you can keep standard cell signal pins out of this via shadow.
In the past I have used vertical soft blockages aligned to all the via stacks.
Now I will try the same thing but allow low pin density cells ( ie.registers ) into the via shadow and keep the nasty cells (ie. aoi222 ) out.
refinePlace should be enhanced to automatically consider / limit the number of signal pins in the via shadow.