I guess by now most of us are already familiar with Rapid Adoption Kits (RAKs). These are packages that include a detailed instructional document and a lab database. You can browse all the available materials at http://support.cadence.com.
Rapid Adoption Kits (RAKs) - The purpose of RAKs is to demonstrate how users can use Cadence tools in their design flows to improve productivity and to maximize the benefits of their tools. Here are a few important RAKs and appnotes that were published recently on the support portal (http://support.cadence.com) which might be of interest to many of us!
This content helps us learn gigascale prototyping with FlexModels and presents a prototyping usage model. FlexModels enable gigascale design exploration using the Encounter Digital Implementation (EDI) System.
2. RAK - Introduction to EDI System 13.2 & Block Implementation Flow
This RAK can be extremely helpful for beginners who intend to learn the EDI System. RAK includes EDI command and graphical user interface (GUI), how to set up the EDI system, and how to implement the flat flow that can be used for chip or block Implementation
3. RAK - Basic Floorplanning in EDI System 13.2
This knowledge piece helps us learn how to specify the floorplan, move and edit placement constraints, create placement and routing blockages, create power and ground rings and stripes, and power routing
4. RAK - Power and Rail Analysis Using Encounter Power System (EPS) 13.1
This material provides information on to know how to do library characterization, analyze VCD files for windows of high signal activity, do static and dynamic power analysis, analyze current/power plots, perform what-if analysis & analyze various rail analysis plots
Time budgeting for very large timing-critical designs using virtual optimization is not accurate enough. With design sizes growing to over 300 million instances, obtaining accurate time budgets with better accuracy for timing critical design is becoming a necessity for many design teams. This document crisply describes how to obtain accurate time budgets using Active-Logic Reduction Technology (ART) to reduce run-time and memory footprint on timing critical designs. This should help the user achieve accurate timing budgets.
6. Appnote - Constraint Implementation and Validation in Interoperability Flow
The key benefit designers derive by using a mixed signal Interoperability flow and OpenAccess (OA) database is the seamless transfer and implementation of various routing constraints from analog to digital designs. Starting from Encounter Digital Implementation (EDI) 13.2 and Virtuoso 616, it is not only simple to create these constraints, but it is also easy to import or export them from one environment to another. Once the design is implemented using these constraints, you can use the Physical Verification System-Constraint Validation (PVS-CV) utility to validate whether these constraints are implemented correctly.
This document is targeted to users who want to apply context constraint for cells with Encounter Digital Implementation System (EDI System). It will introduce how to define edge types and the requested spacing rules, how to assign the specified edge types to cells, and how to spread cells with specific edge types to satisfy the spacing rules. It includes recommendations for a successful chip implementation.
8. Appnote - How to Detect and Fix Isolated Cut Via Violations
This content is meant for users and designers needing to locate and fix isolated cut violations in their designs, and CAD engineers wishing to implement such a flow using the Encounter Digital Implementation (EDI) system. This document provides some background to the problem, and a methodology for resolving violations by inserting multi-cut vias.
9. Appnote - Current Mode Virtual Attacker
Modeling small attackers accurately and efficiently is an important factor in the accuracy of noise and noise-on-delay analysis. This application note explains how the current mode virtual attacker is formed and used.
If you want to insert end caps into the design with Encounter Digital Implementation System, this content should help you achieve your goal. It will introduce you to various end cap insertion and verification methodologies recommendations from Cadence for a successful chip implementation.
This document describes the path exception priority rules which are followed by Encounter Timing System (ETS) / Encounter Digital Implementation (EDI) System for finding effective path exception for a path, among the multiple path exceptions specified for that path. Path exception priority rules are explained (in descending order) as per path exception command type and various command options.
Happy Learning !!