My colleagues on the Verification IP
team have been honored to present at the annual "IP '08" conference
this week in Grenoble, France. Unfortunately for me
I'm not able to attend (hence no photo blog or video; sorry), but my colleague Pete
Heller in the Verification IP group has offered to relay the following news
about this growing event.
Q. [Joe] What is IP'08?
A. [Pete] IP'08 is an annual conference put on by Design and Reuse, a
leading IP information clearing house based in France. The show focuses on
IP design, verification and reuse as well as business issues relating to IP
(design IP and verification IP). See http://www.design-reuse.com/ip08/program/
for more details.
Q. [Joe] Please tell me more about the conference host, "Design and
A. [Pete] Design and Reuse (D&R) D&R provides a global
collaboration network for sharing design resources in the electronics SoC
industry. They point out that they are "the world's
largest directory of 6,500 Silicon IPs from more than 400
vendors". (See http://www.design-reuse.com for
Q. [Joe] Why is Cadence presenting at IP'08?
A. [Pete] With the October
announcement of the 5X expansion of Cadence's VIP portfolio, we are now the
leading supplier of verification IP with
the greatest product breadth (no kidding -- recall that we support over
30 protocols now). As such, IP'08 is an excellent venue
for Cadence to show off the new, expanded portfolio to decision makers involved
with IP selection.
Q: [Joe] What papers are we presenting at IP'08?
A: [Pete] Cadence is presenting three papers. The first,
"Automating Protocol Compliance Verification Using Metric Driven
Verification" explains a unique capability of Cadence ' s
Verification IP (VIP), the "Compliance Management System" (a/k/a
"CMS") included with our VIPs. This paper describes why it is
needed and how it works.
The second, "Learning Not to Fear
PCI Express Compliance Using a Predictable, Metrics Driven Methodology"
represents work done by one of our customers, ClearSpeed(tm),
based in the UK. It provides an excellent explanation about the
motivation for using a metric-driven approach as well as the excellent results
ClearSpeed achieved (over 95% functional coverage for PCI Express).
Last but not least, we are also sharing
some best practices in embedded software IP verification, in a paper aptly
titled "Embedded Software IP Verification". In a nutshell, the
embedded software world has been seriously lagging the hardware/ASIC
development world in recognizing the ROI of VIP, but things like the now
infamous iPhone call dropping problem that was found to be caused by a firmware
bug is inspiring new thinking in this space.
Q: [Joe] Who is presenting for Cadence?
A: Our colleagues Gabriele Zarri and Markus Winterholer.
Gabriele, our newest solutions engineer, will deliver the presentations on metric-driven VIP automation
and PCI Express. Gabriele came to us from Yogitech, the original supplier
of the OCP UVC now owned by Cadence. Gabriele has a very strong
background in verification in general, architecting and packaging UVCs in
specific, and he also happens to live in Southern France, so
he is an ideal person to represent Team VIP.
Markus is an expert on hardware-software
co-verification from the ISX team, and thus he is a presenter in a session
devoted exclusively to this topic this
coming Thursday morning. Note that he is being joined by co-presenters
Thomas Schultz from Bosch and Djones Lettnin from Tübingen. FYI, Markus
is actually based in Tübingen, which is just near enough to consider driving to
a mix of autobahn and unbelievably scenic, twisty mountain roads, but I
Q: [Joe] OK, last question, and your chance to give your best Cadence
VIP elevator pitch: what distinguishes Cadence's VIP from other offerings?
A: [Pete] Several things -- the most important differentiators are
found in the sheer number of protocols
supported and the depth of Cadence VIP’s functionality and automation. This
* The unique automated protocol
Compliance Management System (CMS) which automates protocol compliance
* OVM multi-language interfaces are included in all
* Direct support for Cadence’s metric-driven verification (MDV) methodology which is prepackaged with each UVC.
Cadence’s depth leadership also extends
to verification engines—only Cadence provides advanced testbench VIP,
assertion-based VIP, transaction-based acceleration VIP, and Speedbridge
adapters for emulation and in-circuit system validation.
[Joe] I'm sold -- I'll take one of everything! Where do I fax the PO? :-)
Thanks Pete for this briefing on IP '08!
In the near future I'll post debrief interviews of Gabriele and Markus
on their impressions of the event in general, as well as what specific
concerns they heard from attendees about their IP and verification challenges.