Verification has come a long way this past year, the highlight of which is UVM. UVM gives us verification productivity with testbench re-use because of a well defined SystemVerilog coding structure. But beyond UVM, what are the areas that are the most challenging and thus time consuming? We recently asked some of our users this question, and got some interesting answers, which are reflected in the chart below.
The interesting one for us is "Debug the Verification Environment (VE) and Device Under Test (DUT)". While we did not break this down, it did highlight one really important aspect -- that our verification environment is now as complex as our DUT itself, and we need to consider making the full verification environments re-useable, not just the testbench. Just like the productivity we achieve when we use UVM, being able to re-use the full verification environment will be a huge productivity boost. The above chart also shows that "Defining Coverage" and "Create Coverage Model" together takes 35% of the time. Hence reuse of coverage models, especially functional coverage models such as SystemVerilog covergroups and assertions, is also an important requirement of the verification engineers.
The premise is that you write an executable verification plan, which defines your coverage model. It defines your corner cases, it captures your scoreboards and checkers, and it defines all aspects of your DUT in such a way that this entire verification structure can be re-located and used as is, without tweaking any code or modifying parameters when that same DUT is used in another design. Assembly and re-assembly of many components where those mini verification environments have all been pre-verified means you can focus on the new parts of your design.
The latest releases of Incisive Enterprise Manager (IEM) and Incisive Comprehensive Coverage (ICC) facilitate this process by incorporating some advanced and powerful features targeted specifically for such use cases. Specifically, IEM provides a new logical instance feature for VE relocation, and ICC provides OVM/UVM object hierarchy dumping. Together these enable verification engineers to reuse the verification environment and analyze the SystemVerilog functional coverage models within the framework of an OVM/UVM test object hierarchy.
Cadence users can read all about this in our technical paper, "Verification Environment Re-Use". The paper demonstrates how logical instances and OVM/UVM object hierarchy management together greater productivity. Download the paper here, and let us know what you think.