Dr. Kerstin Eder, a Senior Lecturer in the Computer Science department at the University of Bristol, UK, teaches a course on functional verification. In this interview she outlines how the course is structured, what makes for a good verification engineer, and anecdotes of how students are getting snapped up by industry immediately upon graduation.
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Brief digression in regard to the industry demand for her graduates:
Anecdotally I can confirm the high demand for verification engineers -- fresh out of school or experienced -- here in the USA and other geographies. For example, I can tell you first-hand that here in Silicon Valley we are seeing an increase in poaching: a few weeks before DAC I had scheduled a meeting with a verification group based at the Santa Clara offices of a large, world-wide semiconductor company. They had to cancel because two key verification engineers that we were going to meet with had just quit to go to another company!
In short, if you are an engineer or computer scientist between jobs, earning your way through courses and/or training like that offered by Dr. Eder will give you a leg up in this tough economy -- the verification field seems to be about as recession proof as it gets in the technology business. If you can't go back to school, you can get a running start on your own by taking advantage of the many resources introducing the Universal Verification Methodology (UVM). For starters, there is a ton of great, free material on the Accellera UVM World site -- http://www.uvmworld.org/. Cadence has also published two books on verification: A Practical Guide to Adopting the Universal Verification Methodology (UVM) provides a great overview of UVM, and Advanced Verification Topics uses UVM as a framework for functional verification with mixed-signal, multiple languages, low power, metric-driven verification, and more.
Joe Hupcey III
On Twitter: @jhupcey, http://twitter.com/jhupcey
Reference LinkDr. Eder's home page: http://www.cs.bris.ac.uk/~eder/