E-mail reminders for the DVCon 2013 Call For Abstracts prompted me to look through my DVCon 2012 folder -- lo and behold I came across the following video interview. It was shot during the show, but the official approval fell between the cracks and didn't come through until recently. Regardless, the issues raised in the paper that's the subject of the interview (From Spec to Verification Closure: A Case Study of Applying UVM-MS for First Pass Success to a Complex Mixed-Signal SoC Design) are as challenging as ever. Here the paper's author Neyaz Khan, a mixed signal verification R&D manager at Maxim Semiconductor, discusses what needs to be considered when the Universal Verification Methodology (UVM) is extended to support mixed signal verification projects, the implications for circuit modeling, and the optimal R&D team composition.
If the embedded video fails to play, click here.
Note: if you have never attended a DVCon, you can expect to meet design and verification experts like Neyaz everywhere you turn - clearly worth the price of admission!
Question: if you are in the digital-mixed signal field, are you seeing similar trends in your company and/or customer base? Please share your thoughts below, or contact me offline.
Until next DVCon, may your throughput be high and your power consumption be low!
Joe Hupcey III
On Twitter: @jhupcey, http://twitter.com/jhupcey
Reference LinksDVCon 2013 Call For AbstractsNeyaz's DVCon 2012 paper, From Spec to Verification Closure: A Case Study of Applying UVM-MS for First Pass Success to a Complex Mixed-Signal SoC Design
Richard Goering Industry Insights report on the book Neyaz co-authored: "Advanced Verification" Book Brings UVM to Mixed Signal, Low Power, Multi-LanguageMy Photo Essay, Video Playlist, and Comments on DVCon 2012