3D integration is a promising new technology that can potentially save space and power by stacking die in 3 dimensions. I recently spoke with Riko Radojcic, Qualcomm design lead for TSS (Through Silicon Stacking – Qualcomm’s term for 3D ICs), about how Qualcomm is deploying this technology and developing a design environment that can support it. Radojcic was on his way to Nice, France, where he’s presenting a talk on 3D integration and through-silicon vias (TSVs) at an April 24 workshop at the DATE Conference.
Why is Qualcomm interested in this technology? Radojcic said TSS can provide form factors that save board space and power. TSS can also support heterogenous integration with its ability to place digital logic, analog, RF, and memory on different die. As for cost, he noted that TSS is a new technology that is not going to compete with wire bond right way. But the costs may be justified. “If we can save a lot of power, then it may be okay if it costs us a few pennies more,” he commented.
Qualcomm is currently developing its first implementation of what it calls a “stage one” class of TSS products. These consist of a functionally partitioned two-die stack. Combinations could include analog and logic, RF and logic, or memory and logic. In future stages, Radojcic said, Qualcomm expects to design with multiple tiers and more than two die.
Radojcic said that Qualcomm describes the design approach for stage 1 as “2.5D” rather than “3D.” As such, tools need to understand that a die has two sides, but do not need to cope with multiple die. As a result, “we do not need disruptive changes to the design flow,” Radojcic said. But further down the 3D roadmap things change. “If you want to build a 3-die stack or a logic-to-logic stack where you partition across tiers, then synthesis, place and route, and design for test all need significant upgrades.”
Qualcomm uses TSVs for inter-die interconnection. TSVs provide far more density than any other technology, Radojcic said. Currently, Qualcomm is using thousands of TSVs, but future products may have tens of thousands or even hundreds of thousands. But TSVs raise a number of challenges. “They require thinning of the die, which is a large source of concern for us,” he said. “This raises mechanical and thermal concerns.”
TSVs also raise design challenges. Where do you place the TSVs, and how do they impact the rest of the design? To enable 3D design with TSVs, Qualcomm is working with its partners to develop a flow that consists of three methodologies:
Test is another looming issue. “So long as partitioning is done along functional lines, it’s not big,” Radojcic said. “But when you start partitioning logic across tiers, the test challenge becomes significant.”
TSS will require IC/package co-design. It will require rules or models that make chip designers aware of constraints. “The beauty of TSS is that it blurs the lines between packaging and silicon design,” Radojcic said. “TSS, by definition, is the integration of these.”
Collaborative partnerships are a crucial part of Qualcomm’s work on 3D ICs. For example, Qualcomm is working with Cadence on thermal solutions, and Radojcic said the Cadence collaboration and Qualcomm’s use of the Encounter Digital Implementation System helped Qualcomm produce its first TSS test silicon.
Qualcomm’s staged, collaborative approach to 3D IC design appears to be paying off. “We are developing products for our first implementaiton,” Radojcic said. “We are working with a number of key partners in our supply chain.”
Well, the 3D IC technology is gaining momentum. I wonder how much it will take for this technology to become a standard in consumer electronics (I mean, TSV-based electronics).