Since the User Track (sponsored by Cadence) was new at this year’s Design Automation Conference, I thought I’d attend at least one session to see what it’s all about. The Thursday morning session, “Power Analysis and IP Reuse,” brought forth some interesting practices that should interest any design team concerned with power issues.
This was a paper session, and here’s a brief snapshot of the papers:
Dynamic Power Analysis for Custom Macros Using ESP-CV, Qualcomm. Power simulation for custom macros is typically done with a transistor-level simulator, a slow practice that compels designers to work with 100-cycle windows. Qualcomm figured out how to use an equivalence checker to run power analysis for macros. Authors say it’s sufficiently accurate, and is fast enough to run tens of thousands of cycles.
Power Supply and Substrate Noise Analysis; Reference Tool Experience With Silicon Validation. Kobe University, ARTEC, STARC, Apache Design Solutions. This team built a 90 nm CMOS test chip with a 32-bit processor, added probe locations, and measured on-chip noise. The measurements were correlated with simulation. The team established that adding substrate noise analysis greatly enhances the accuracy of full-chip noise analysis. Off-chip network modeling is important, too.
Modeling and Design Challenges For Multicore Power Supply Noise Analysis, IBM. Multicore SoC design complicates power distribution noise analysis. This paper looks at modeling strategies for multicore power networks and shows simulation results.
Dynamic Power Noise Analysis Method for Memory Designs, Samsung. This paper discusses the challenges of power noise analysis in memory design, and the use of current-source models to detect it. The current-source approach reduces run times and makes it possible to simulate multi-bank operation.
Hard IP Reuse in Multiple Metal Systems SoCs, Texas Instruments. This paper is not about power modeling, but is about hard silicon IP reuse in multiple SoCs. The paper describes over-the-block (OTB) routing, and describes “best practices” that allow both IP creators and IP integrators to take advantage of it.
Di/dt Mitigation Method in Power Delivery Design and Analysis, Intel. On-chip, dynamic power integrity simulation allows physical designers to mitigate di/dt issues. While the simulator is intended for post-layout analysis, it can also be used in the early stages of the design cycle.
Cool stuff, and I’m sure the other 8 User Track sessions were also interesting and valuable, not to mention the poster session and ice cream social Wednesday. Other sessions looked at design and test, physical design, front-end verification, timing analysis, front-end design productivity, embedded software and design exploration, front-end power planning, and analog/mixed-signal design. Grant Martin’s Taken for Granted blog has a report from the embedded software and design exploration session.
The User Track papers are not in the DAC proceedings, but I’m told the presentations will be available at the DAC web site, probably about a week following publication of this blog posting.
User Track organizers Leon Stok (IBM) and Soha Hassoun (Tufts University) did a good job of organizing what must have been a monumental task. It’s this kind of practical, user-to-user communications that will keep conferences like DAC on the map.