A stark warning about SoC development costs was sounded in a panel discussion on the “Economics of Next Generation SoCs” at the recent EE Times virtual System-on-Chip Conference. Development costs are not only high, said Ron Collett, CEO of Numetrics, but are “significantly underestimated” in most cases, thus invalidating the business decision to go with an SoC in the first place.
To justify the investment in an SoC, Collett said, the available revenue stream must be 10X the development costs. Thus, if an SoC has a $500 million market opportunity, development costs should not exceed $50 million. Today, however, development costs can easily reach $40 to $80 million. Collett noted that 60 percent of this cost is labor and that the major part of the overall development cost is verification.
“There is an assumption of productivity that is much higher than what is actually achievable, and we see that all over the industry,” Collett said. What about manufacturing and mask costs? Collett responded that most semiconductor companies are going fabless or fab-lite, and that the “development cost is the dominant factor in figuring out the business equation.” As a result of high development costs, he said, many Numetrics customers are doing fewer SoC designs.
Numetrics is in a good position to make these observations. The company offers software solutions that help semiconductor companies plan chip development projects, develop schedules, measure risks, and identify engineering resource shortfalls.
No one on the panel disagreed with Collett. “Engineers are eternal optimists,” said Steve Douglass, vice president of product development at Xilinx. “They will tend to under-estimate how long it takes to get the job done.” Grant Martin, chief scientist at Tensilica, added that a good part of the SoC development cost is embedded software development and verification.
Anyone who has ever been involved in a home remodeling project knows how hard it is to get a reliable estimate up front of how long it will take and how much it will cost. Underestimating time and cost is commonplace. A large SoC design project is far more complex, with many more stakeholders. There is no simple answer to the question of how development costs can be accurately predicted. But there are some ideas about how to lower development costs.
One solution proposed by panelists was silicon-proven IP. Martin, for example, advocated the use of configurable processor IP. Sven Andersson, ASIC designer at Realtime Embedded AB, said that “well proven” IP can significantly reduce the verification task.
Xilinx’ Douglass noted that high SoC design and mask costs are driving many companies towards programmable platforms such as FPGAs. Andersson noted that his company is using more FPGAs than in the past, but he observed that “there are still places where you have to go with an ASIC. It is hard to get power down and get a small size without an ASIC.”
Collett said that semiconductor companies are using programmable architectures and are relying more on embedded software for differentiation. He added, however, that “software is not a panacea – the cost of software development is skyrocketing.”
Panelists briefly discussed ESL, but did not, in my opinion, really close the loop and consider how ESL can reduce SoC development costs. A transaction-level modeling (TLM) based design and verification flow, as described in a recent Cadence announcement, can provide a number of productivity advantages. Design creation is faster, golden source has less code and fewer bugs, simulation is potentially orders of magnitude faster, and silicon IP can be used without micro-architectural changes. All these advantages translate into reduced development costs.
Of course, anything new and different has some initial costs. But as is the case with home remodeling jobs, investing in better tooling that improves your productivity can pay for itself very quickly.
A previous blog describes other portions of the virtual conference.
Great article. The analogy to home remodeling is a good one. And while the focus of this panel is on development costs, the "materials" costs and tradeoffs should also be considered. What IP should it use? What would the area overhead be for a certain power architecture? What package would be required if the chip were implemented this way? How challenging will timing closure be at this frequency/process? Examining all of these tradeoffs along with the economic impact using something like the InCyte Chip Estimator should go hand-in-hand with estimating the development costs.