Well-made process design kits (PDKs) are critical for successful IC design, and design teams should keep in touch with PDK technology development, according to Kristin Liu, principal CAD engineer at National Semiconductor. In an interview at the recent CDNLive! Silicon Valley, she talked about the challenges of PDK development and explained “model playback,” the topic of her CDNLive! paper.
Liu is involved in PDK development and automation, project management, customer support, PDK methodology and flow definition, circuit modeling, benchmarking, and new CAD tool implementation. She is working on BiCMOS processes for the analog ICs that National develops. National’s PDKs include customized schematic symbols, parameterized cells (Pcells), verification runsets, customized utilities, mask design libraries, and standard cell libraries. The PDKs are used in the Cadence design environment.
In the video clip below, Liu talks about the challenges of PDK development, the need for accurate device characterization, and National’s use of the Cadence Spectre simulator.
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Liu’s CDNLive! paper was entitled “A Conventional Model Playback Utility In The Cadence Design Environment.” Model playback, she explained, is a utility developed at National Semiconductor that lets designers examine how a model behaves in real time. It lets designers “play back” the device characterization with customized design specifications. Designers can compare device behaviors among different processes, validate the model with different simulators, or view the model accuracy between the simulation results and the silicon measurement data, all in real time.
Liu has some words of advice for the IC design teams who rely on PDKs. “As an RF IC designer myself earlier, I felt frustrated and helpless with PDK issues,” she said. “Now I realize that it is important for designers to be involved in the PDK methodology definition. I’d encourage designers to work as closely as possible with PDK developers for feature enhancements, demos, design guides, design automation, and design flow benchmarking. This will maximize design productivity and reduce human error.”