At the Cadence Mixed-Signal Design Summit, held Oct. 27, I had a hard time finding a seat in a packed auditorium. One reason for the summit’s popularity was its hands-on, practical nature. A series of user presentations showed how designers are solving real problems in mixed-signal verification. Below are quick summaries of five such presentations.
Jess Chan (Qualcomm), Robert Milkovits (Jazz), Prasanth Aprameyan (Micron), Kumar Abhishek (Freescale), and Yuval Shay (STMicroelecrtronics) presented at the Mixed-Signal Design Summit (left to right).
Top-down approach guides mixed-signal simulation
Yuval Shay, staff engineer for mixed-signal verification at STMicroelectronics, gave a presentation entitled “Mixed-language simulation of sigma-delta ADC with AMS Designer.” In the presentation, he outlined a “top-down” hierarchical verification methodology that uses the Cadence Virtuoso AMS Designer simulator within the Virtuoso Analog Design Environment (ADE).
The idea behind the top-down methodology is to start verification as soon as the design effort starts. To accomplish this, engineers create models at the highest level possible and slowly expand the hierarchy “downwards,” substituting behavioral models with transistor-level models until full-chip, transistor-level simulations can be executed. The same testbench developed for the behavioral level can run the full transistor-level design.
Shay identified three basic steps to ST’s methodology:
Shay said this approach has “proven to be a very good solution” for his company’s needs.
Modeling methodology moves real numbers
Simulating real number traffic is an important part of mixed-signal simulation, but there are some tricks to it, according to Jess Chen, senior staff engineer at Qualcomm. His presentation was entitled “A modeling methodology for verifying functionality of a wireless chip.”
There are some challenges with real number traffic in event-driven simulations, Chen said. He prefers a “baseband equivalent” approach that passes multiple real numbers on a single wire. Advantages: the models run fast by suppressing the carrier, they produce realistic signals at the DAC outputs and ADC inputs, IQ swapping is easy to detect, and noise is easy to include.
Chen said his group considered various options for simulating real number traffic, and used a PLI function. This makes it possible to pass real vectors between Verilog modules, use bidirectional real number traffic, switch between voltage and current on the fly, and use a resolution function for real number drivers. Qualcomm applied this methodology to a wireless SoC and found over 100 functional bugs before tapeout.
Full chip Spice simulation really does work
Think full-chip Spice simulation is impractical? Kumar Abhishek, senior analog and mixed-signal design engineer at Freescale Semiconductor, showed how it can work in a presentation entitled “Full chip Spice simulation methodology for zero defect silicon.”
What Abhishek described is actually a Verilog-AMS/Spice co-simulation approach. In a microcontroller SoC, he used Spice models for blocks such as ADC, DAC, voltage regulator, LCD controller, and clock generator. Verilog-AMS models were used for a crystal driver, analog sensor model, and supply driver. Verilog-AMS monitors were used for display, clock profile, data converter, and power monitor.
Abhishek showed a list of microcontroller verification challenges, including those related to analog behavior, power management, and pad rings. He said the AMS/Spice co-simulation approach is “robust” or gives 90 percent confidence in most cases. He also showed a number of test cases and talked about setup times and simulation run times. For example, in a test case with 6M transistors, power-up simulations took a setup time of 2-3 days and a run time of 15 hours.
He concluded that the proposed full-chip Spice methodology is useful for catching corner cases for complex mixed-signal SoCs, especially in complex power-gating scenarios. Abhishek noted, however, that it is “not a replacement” for the existing SoC mixed-signal verification flow, but a complement that can help attain 100 percent coverage for complex protocols.
How to capture design intent
Robert Milkovits, director of technical support at Jazz Semiconductor, gave a presentation entitled “Capturing AMS design intent.” He first spoke of “design intent holes and misses,” including:
Milkovits talked about how Cadence Virtuoso platform updates in IC6.1 help users represent design intent. He noted that constraint management is integral to design intent, and showed how Virtuoso constraints help “address both the big picture and the design details.”
A look at flash memory verification
Prashanth Aprameyan, senior verification manager at Micron Technology, spoke on “Mixed signal verification – a NAND memory perspective.” He said that NAND memory verification is very similar to other mixed-signal verification, and noted that “for us, verification cost is as important as design cost.”
NAND flash memory includes a memory array, sense amplifiers, high-voltage circuits, controller and logic, and low-voltage analog, pad and I/O. Micron uses both Verilog-A and digital Verilog modeling of the memory array. The Cadence Virtuoso UltraSim simulator, a fast Spice simulator, is extensively used for NAND flash verification. Micron is also investigating wreal behavioral modeling with Verilog-AMS.
Apremeyan noted that full-chip simulation time is becoming prohibitive, that it would be nice to have all electrical aspects of verification under a single tool, and that design for yield (DFY) analysis in fast Spice would be helpful.
In a Q&A panel following the presentations, panelists fielded questions on the difficulty and cost of developing analog behavioral models, whether designers should do their own verification, modeling for performance verification, SoC-level and IP challenges, and test.
The summit also featured a keynote by Paul Emerson, general manager for the analog and logic business at Texas Instruments, and several presentations on Cadence’s mixed-signal solutions. Videos will be available on-line in November. Another review of the summit can be found in Paul McLellan’s blog.