Double patterning lithography, which splits designs into two or more masks, will probably be required at 22 nm and below. The plus side is that it will extend current optical lithography equipment to yet another process generation. But it will also add some costs, require new EDA tool capabilities, and most likely place some restrictions on IC layouts.
To get a perspective on double patterning, I talked to Jason Sweis, senior product engineering manager at Cadence and our resident double patterning expert. He explained that double patterning extends 193 nm lithography by splitting patterns that would be too dense to print into separated, spaced-out patterns that are easier to print. This is accomplished by making multiple exposures using two or more masks. The mask images are recombined on the wafer during processing. The resulting image is the original design target before decomposition.
Jason said he thinks double patterning will come into play more frequently at 28 nm and below, although someone who has a lot of high-end equipment might be able to delay it a little longer. It will be needed for all lower critical layers up to a few metal layers. When extreme ultraviolet (EUV) lithography comes on line, it may no longer be needed, but the timetable for EUV is still uncertain.
There are several approaches to double patterning. There are various categorizations, but here’s Jason’s view:
Jason noted that SADP is widely used today by flash memory manufacturers, and that many customers like it because of its self-aligning capabilities. While Litho Etch Litho Etch could result in errors due to overlays, SADP will not. Now, he said, the challenge is to expand SADP beyond the small, repetitive cells of flash memory to DRAM and logic.
What routing restrictions will SADP pose? The best layouts for this technique are on-grid and unidirectional. Jogs and off-grid features will make double patterning more difficult. Jason noted, however, that “we hope to minimize the amount of restrictions that are going to be imposed.” And since foundries are generally talking about restricted design rules (RDRs) at 32 nm and below anyway, it is unclear whether additional rules will be needed.
Other concerns may be greater. One is die size, which will probably be slightly increased, but this has not yet been quantified. Another is cost. With double patterning, you’ll need two or three masks, although if a third mask is required it probably won’t require immersion. Throughput on steppers will be slower, yields may be lower, and optical proximity correction (OPC) time and cost will be doubled where two masks are employed.
There will also be some additional EDA tool requirements. Specifically, tools will be needed for decomposition, which involves taking the original design intent and formulating the masks. Geometry processing and verification of the final masks will also be required. Jason said that current efforts are aimed at rule-based decomposition, which runs quickly and doesn’t require calibrated models. A designer would want a DRC-like tool before tape-out to make sure the layout is manufacturable.
Since most chip design teams won’t be affected by double patterning until 28 nm or 22 nm, I was surprised to learn that Cadence already sells a solution for SADP. It turns out that Cadence is engaging customers who are developing their next generation technology nodes when design rules are still fluid. This provides an opportunity to help define the technology and tools needed before double patterning hits the mainstream, and establishes deep partnerships with customers.
The primary users right now for SADP are flash memory providers. Double patterning is a small market today, but it looks like it will become a much larger market within a few years. Whatever the costs, double patterning will be a more available and less expensive solution than buying EUV equipment for quite some time.
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