Traditional synthesis flows aren’t keeping up with IC complexity and low-power demands, according to Laszlo Borbely, design engineer at Micron Technology. At the recent CDNLive! Silicon Valley, Borbely discussed a new flow that uses concurrent multi-mode synthesis and low-power optimization based on the Common Power Format (CPF). He showed how the new flow worked on a memory controller IC.
The traditional flow, Borbely explained, employs bottom-up synthesis for separate submodules, where submodule I/O delay is budgeted for the worst case. Top-level synthesis is constrained to satisfy the worst-case mode, thus over-constraining the overall design. Power structures are added later, with power shutoff (PSO) simulation delayed until the netlist is available. Test structures are added later as well.
In the new flow, PSO can be simulated at the register-transfer level with CPF. Synthesis is top-down and does not require module-level constraints. With multi-mode synthesis, the top level is properly constrained for each mode, not the worst-case mode. Power and test structures are added during synthesis.
The main result is that the design is not over-constrained, and area is not wasted. Also, since power and test are added during synthesis, timing is more likely to be correct before place and route. Isolation and PSO cells can be inserted automatically, and equivalence checking can be automated and driven by the CPF file. Tools used in Micron’s flow include the Cadence RTL Compiler, Conformal Logic Equivalence Checker, Conformal Low Power, and SoC Encounter.
In the attached video clip taken from an interview after his presentation, Borbely discussed the need for multi-mode optimization, problems with the existing synthesis flow, the role of CPF, and the advantages of the new approach.
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Borbely has some advice for implementing a multi-mode optimization synthesis flow. “It is probably most successful if the functional modes are described in detail, and each mode is specified as simply as possible,” he said.