As noted in a recent Cadence blog by Tom Anderson, the Accellera Verification IP (VIP) Technical Subcomittee has voted to make the Open Verification Methodology (OVM) the basis of its upcoming “Universal Verification Methodology” (UVM) standard. Here are some thoughts about what this means, why it’s important, and what questions will need to be answered as the UVM standard unfolds.
First, why is a methodology needed? Because the SystemVerilog language description alone does not tell you how to build testbenches or verification IP. Thus, early SystemVerilog users developed in-house methodologies. Synopsys then launched the Verification Methodology Manual (VMM), and Cadence and Mentor Graphics collaborated to produce OVM, which is now available from the very active OVM World web site.
With two different methodologies in the marketplace, many users were faced with having to juggle VMM and OVM VIP and/or testbenches in the same simulation environment. Amid widespread agreement that standardization was needed, the Accellera VIP committee was formed. It was launched with two goals:
Accellera’s decision to use OVM as the basis for the UVM standard is a great validation for OVM, which has already attracted more than 50,000 downloads. Until now, as Tom Anderson noted, some users were still sitting on the fence, unsure which methodology to use. “We think this [vote] removes all question marks,” he told me. “Anybody who hasn’t adopted OVM should feel completely comfortable adopting it.”
That said, the development of UVM is just beginning and there are many questions to be answered over the coming weeks and months. For example:
As I noted in a recent blog, true VIP interoperability goes far beyond standard methodologies and class libraries. But a standard is essential for interoperability to be possible. With its latest decision to move forward based on OVM, the Accellera VIP subcomittee is making great progress towards solving the VIP interoperability challenge for SystemVerilog users.