Every IC design team does it. Most don’t have a name for it and most don’t use automated tools. It may not show up on flowcharts depicting the IC design flow, and most EDA vendors pay little attention to it. But it’s an absolutely critical part of the IC design flow that can make the difference between success and a very expensive failure.
The answer to this riddle? Chip planning. Not “floorplanning” as we’ve known it for years, but “chip planning.” There is a difference, as I will explain.
There is no dictionary definition of chip planning. But Adam Traidman, general manager of chip planning solutions at Cadence, has what I think is a pretty good definition – a “pre-RTL what-if analysis that looks at the interrelationships between various architectural options, and their impact on size, power, and the cost of the chip.” In other words, you start with some basic information about your process and your silicon IP, and end up with size, power and production cost estimates before writing any RTL.
This is quite different from floorplanning, which generally starts with a netlist and does some preliminary placement and routing. Floorplanning allows back-end designers to do an initial check on physical implementation. The chip planning process may result in a “seed” floorplan, but it’s developed by front-end designers at the pre-RTL level. This seed floorplan can provide a good starting point for the back-end crew.
Perhaps the most interesting feature of chip planning is the potential to get cost estimates before architectural decisions are finalized. I wrote in a recent blog that reducing design costs will be a major focus for EDA customers and vendors in 2010. You can only reduce costs if you can estimate them. Indeed, in another previous blog, I reported a panel discussion in which it was noted that SoC development costs are chronically underestimated.
Today many design teams do ad-hoc chip planning with Excel spreadsheets. Excel is free, but there are some disadvantages. Excel isn’t hooked up to a database of commercial IP components, it doesn’t have any foundry process information, and it doesn’t allow a rapid, what-if analysis with power, area and cost estimates.
The Cadence InCyte Chip Estimator is a chip planning tool that leverages a database of 7,000 commercial IP components, and provides die size, power, performance achievability, and production cost estimates. I have a lot more to say about chip planning and InCyte Chip Estimator in an article in the January 12 ChipEstimate.com newsletter. The article includes some comments about the use of the tool at Integrated Device Technology (IDT).
Expect to hear a lot more about chip planning in 2010 and beyond. In this economy, companies can’t afford to skip over this increasingly vital step.
Thanks for providing a capsule on this term, Richard! While there has been talk and work on power estimation in ESL (how much of each, who knows?), the physical consequences of a design have not been touched in that topic. Maybe not a surprise, with all of the fundamental development work (SystemC standard library, TLM, etc.) that was needed. Area and cost may not be the first worries up front, versus performance and power, but one would wonder once faced with synthesis (automated or custom RTL development) for implementation of your high level design!