conditions are looking up for the EDA and semiconductor industries, but
customer concerns have shifted, according to Lip-Bu Tan, president and CEO of
Cadence. At a DVCon keynote speech Feb. 24,
Lip-Bu described a new landscape in which EDA providers must help customers be both
productive and profitable in the face of escalating complexity and soaring
design costs. This calls for a different approach to end user product
development, and new role for the EDA industry.
was entitled "Breaking through the efficiency barrier." What follows is my list
of takeaways from the broad-ranging, 40 minute speech.
Conditions are improving for the
industry is improving. In the last six months there's been a sea change,"
Lip-Bu said. After visiting 300+ customers, Lip-Bu said he's seeing more new
project developments. He noted that at least 10 semiconductor companies are
planning to go for IPOs this year, possibly creating some momentum in which VCs
will start investing in semiconductor startups again. "I'm very excited about
this industry and I think we have a great opportunity going forward," he said.
Some new growth drivers for end
visits customers, Lip-Bu noted, he spends a lot of time trying to understand
their products and end markets. He believes there are some exciting growth
drivers that will create opportunities for EDA providers. Specifically, he
called out 4G communications, cloud computing, and mobile video. Such
applications will demand low-power and mixed-signal design expertise.
Semiconductor vendors now
responsible for software stack
companies are becoming software companies. Lip-Bu talked about a fabless
semiconductor provider in the wireless market that has hired over 1,000
software developers and is developing the entire software stack for its
products. As a result of such efforts, he said, concurrent hardware/software
development is becoming very important.
Design costs are threatening
A new SoC
development project may cost $100 million at an advanced process node, Lip-Bu
said, meaning that 80 million units may need to be shipped for a company to
attain profitability. This is a tremendous risk. "It's not just about
productivity," Lip-Bu said. "It's about design costs, profitability, and time
to market. Our job is to ensure that the customer becomes profitable in their
Closing the productivity gap
still a gap between silicon capacity and engineer output. How can we close it?
On the design side, Lip-Bu said, it's time move to the transaction-level
modeling (TLM) level of abstraction. On the verification side,
hardware/software integration and IP reuse are critical. On the implementation
side, new technology must embrace challenges such as giga-gate complexity,
design for manufacturability, and mixed-signal design.
Closing the profitability gap
can be achieved if customers efficiently "Create, Integrate, Optimize." The
Create stage should produce "integration ready," silicon-proven IP designed at
a high level of abstraction. The Integrate stage depends on "open IP access"
and rapid SoC integration. Hardware/software convergence is very critical in
this phase, along with cost-effective verification. The Optimize stage brings
in die, package, and test automation. This phase will rely on expertise in
mixed-signal design and package design, both areas of strength for Cadence.
Criteria for successful acquisitions
that any prospective acquisition should involve three things. These include a
team that brings value to Cadence, a product that strategically "makes sense,"
and customer traction that can be built upon and expanded. "If all three are
right and the pricing is right, we'd love to do it," he said.
to the customer is the best way to find out where any industry is going. With
300-plus visits in a little over one year - no, more than that, because some
companies were visited multiple times - Lip-Bu has gained a unique perspective
on where the electronics industry is headed, and what the EDA industry must do
to support it. I hope EDA providers and customers alike will shake off the
doldrums of 2008-2009, and share some of the excitement Lip-Bu feels about the
Note: Photo taken by Joseph Hupcey III
"This phase will rely on expertise in mixed-signal design and package design, both areas of strength for Cadence." -- Lip-Bu
I, as a principle EDA engineer, evaluated Cadence Mixed-Signal product two times (using real designs) in last five years at a CPU company and an analog company, both time the Cadence product shown clear advantage, and the product team has very strong members.
So, I agree with what Lip-Bu said. Wish Cadence continue lead the way.