Two Design Automation Conference panels that you probably haven't heard off address two of the hottest issues in electronic design today. One panel focuses on 20nm design challenges, and the other tackles the perennially tough topic of mixed-signal verification. Both are free and organized by Cadence, and the 20nm panel even comes with a free lunch.
The panels are described below. I would also like to bring your attention to the Cadence EDA360 Theater located at the Cadence booth, #2237. The theater provides three days of presentations from customers, partners, and Cadence representatives. You'll find a schedule here. A description of all Cadence activities at DAC, including conference speakers, demo suites, the Denali party, and the "I Love DAC" campaign can be found at our microsite here. And don't forget to download the free Cadence DAC iPhone app.
Getting a Jumpstart on 20nmMonday, June 6, 11:30 am - 1:30 pmOmni Hotel Grand Ballroom Salon D (Level 4)
Power, complexity, lithography - the challenges at 20nm are daunting. This panel brings together IP providers, semiconductor companies, and a Cadence representative to discuss the challenges of 20nm design and implementation, and the approaches needed to ease the challenges.
The moderator is Jim Handy of Objective Analysis. Panelists are:
Further information and registration is available here.
Stop thinking and start acting: methods to shrink the verification deficitWednesday, June 8, 12:00 pm - 1:00 pmCadence EDA360 Theater, Booth 2237
On Wednesday June 8, I will moderate a panel on mixed-signal verification at the EDA360 Theater. Three user panelists will discuss why mixed-signal verification is so challenging, talk about how they're addressing those challenges today, and suggest advancements in EDA tools and methodologies that can help resolve the challenges. Panelists include:
If you're coming to DAC, please come to either or both panels and bring some good questions.