What challenges are users facing in front-end IC design these days? According to presenters at a Q&A panel session at a Synthesis Community Event at Cadence Dec. 8, power minimization and optimization are at the top of the list.
The panel included three user presenters, an ARM executive, and a Cadence R&D representative. Each of the three user presenters had previously given a separate presentation. Panelists were as follows, shown left to right in the photo below:
The panel was moderated by Steve Carlson, engineering group director for front-end design at Cadence. Prior to the panel, Adel Khouja of Cadence talked about modern synthesis trends and challenges, as reported in my previous blog post.
Power on Top
Carlson started the panel discussion by asking how design methodologies will change in the next 2-3 years. Given that every user presentation focused on low power design, as did Heinlein's presentation, the answers were not surprising.
"Power is pervasive in everything we do," Heinlein said. "There's a lot of work targeting leakage and dynamic power, and we're seeing power management baked into designs in places where it wasn't present before." In particular, he noted, clock power has become a serious problem.
"I agree that power is the main problem in design," Natarajan said. One trend he's seeing is the move to 2.5D and 3D die stacking. However, tool support is just getting started, he said.
In consumer electronics, Wong noted, time-to-market is shrinking just as complexity is going up. Power is a major factor in that complexity. "We have to use multiple power modes and multiple power domains," he said. Borbely-Bartis commented that power-efficient designs are becoming more and more important, and time-to-market is shrinking, leading to the increasing use of third-party IP. "In the long term," he added, "I would not be surprised if the RTL is generated by tools."
Giomi noted that power, performance and area (PPA) will continue to be a focus for front-end tools. Trends over the next couple of years include increasing physical awareness, and a growing need to handle greater complexity and capacity.
Will Front End Design Disappear?
Wong made the point that front-end design is experiencing a "split." He observed that part of it is being integrated into the design flow on the RTL side, and another part is becoming more integrated with the back end. "When we do synthesis with multiple power modes and a lot of other constraints, we are actually saving time on the back end," he said.
Carlson picked up on this theme by asking whether RTL synthesis will be absorbed into the back end, resulting in an RTL-to-GDSII tool, or whether high-level synthesis will replace RTL synthesis. Several panelists observed that different design sizes and styles will have different requirements, with some chips or blocks calling for physical-aware synthesis while others do not.
Wong said that designers are doing a lot more low-power checking and timing checking, thus saving time in the front end. "On small size designs we see the front end starting to disappear a little bit in terms of schedule and importance," he observed. He also noted that "we try to cut turnaround time between the front end and the back end. If we have to go back to the designer to change RTL code, that is a nightmare."
"In the early phases of design you need a very quick turnaround," Borbely-Bartis said. "For production, you should provide as much physical information as you can. I would see synthesis as part of place and route."
Carlson asked how many audience members think synthesis will become part of the physical design flow. Around 30-40% raised their hands. He asked how many think synthesis will be more closely tied to C language modeling and verification. Perhaps 10% raised their hands. "I don't think these are mutually exclusive," Heinlein said. "Everybody has to care about physical issues."
Questions and Concerns
Several audience members offered questions or comments during the panel. One asked whether SystemVerilog is being used for RTL design, and Giomi noted that Cadence is seeing increasing use of SystemVerilog for this purpose. Another commented that the most important aspect of synthesis is a fast turnaround time.
Another audience member asked if there's any way to qualify, or get a "stamp of approval," that third-party IP is good. "I'm on the GSA working group on that topic," Heinlein said. "The simple answer is that there isn't a standard."
The panelists had previously offered the following presentations:
The event also included technology demonstrations, lunch, and a reception with Cadence R&D. All in all, it was a very powerful half-day event for users of RTL synthesis tools.