Complex analog/mixed-signal ICs pose many power grid design and analysis challenges. Unanticipated IR drop and electromigration problems are commonplace, and they significantly impact circuit behavior. But as a recently archived webinar shows, there are a number of ways to minimize these problems, even for advanced-node, mixed-signal systems on chip (SoCs) with hundreds of millions of transistors.
The webinar is titled "Power Integrity Challenges in Mixed-Signal Designs," and is presented by Harish Kriplani, R&D group director at Cadence. Topics include static and dynamic estimation, simulation methodologies, electromigration rules, hierarchical analysis, "what if" rail analysis, and IC chip/package co-design.
Kriplani started by noting the complexity of advanced-node chips that may have hundreds of millions of transistors and multiple power domains. This, he said, creates a need for hierarchical design, in which you analyze a block and create an abstracted view to use at the next level. He also stressed the importance of early power planning, allowing designers to make "aggressive changes" as early as possible.
A mixed-signal, IR drop and electromigration flow is shown at right. Based on the Cadence Virtuoso platform, this flow includes layout-versus-schematic (LVS) and the extraction of signal and power rail parasitics. It includes SPICE or Fast SPICE circuit simulation and analysis, and makes it possible to graphically display results for easier debugging. Finally, it can create an abstract model with a "power grid view" for analysis at the next level of hierarchy.
Following are some of the issues addressed in the webinar.
Static and Dynamic Estimation
Most webinar attendees were probably familiar with dynamic current estimation, which is really just time-domain analysis in SPICE or Fast SPICE. Static estimation, while much faster, is not as widely known in the analog/mixed-signal world. Here, you partition a circuit and identify logic gates or cells based on pattern recognition. You propagate switching activity through the circuit, or a user-specified power-per-cell, to capture an average switching rate. Using both of these methods can be very powerful - and the static approach may be the only choice for large designs.
Simulate Netlist and P/G Parasitics Together - or Separately?
For IR drop/electromigration analysis, the most accurate approach is to simulate the netlist and the power/ground parasitics together in SPICE or Fast SPICE. This is slow. An alternative is a two-part methodology in which you first simulate the netlist assuming ideal power/ground nets, and then solve the power and ground grids with a separate solver. Kriplani showed how to use these approaches and noted that results from both methods correlate to within 10 percent.
Using Block Abstractions with Power Grid Views
From a hierarchical perspective, you want to analyze a block and create an abstract model of the block that can be brought into full-chip power integrity simulation. Kriplani showed how do this by creating a "power grid view" that includes interfaces and ports, internal transistors, decoupling capacitors, and static or dynamic current distributions. The result: "when you solve the system you are essentially doing a flat analysis."
IR Drop Impact on Circuit Behavior
IR drop can affect circuit behavior significantly. In a digital design, this can be understood by bringing IR drop information into a digital timing tool. For small custom designs, you can simulate the netlist with the power grid parasitics. For larger designers, you can estimate block boundary conditions from a full chip simulation run, and resimulate selected blocks with netlist and grid parasitics.
"What If" Rail Analysis
What-if analysis can be employed for any design that has not gone through full optimization. What-if sensitivity analysis highlights areas where the power grid can be optimized for IR drop. What-if analyses can be used for scaling resistance, capacitance, and currents to understand impacts on IR drop.
If you combine a package with high inductance, a chip with high capacitance, and a power grid designed for low resistance, oscillation may result. Thus, a chip-package resonance analysis is needed. I/O noise analysis is also important.
Cadence Power Integrity Analysis Solution
Only at the end of the webinar did Kriplani provide details about the Cadence power integrity analysis solution. On the digital (Encounter) side, it includes the Encounter Power System (EPS), which can provide full-chip static and dynamic analysis. On the custom/analog (Virtuoso) side, it includes the Virtuoso Power System (VPS), which provides static and dynamic transistor-level analysis.
In a demo, product engineer Rose Li showed how engineers can use VPS to simulate and analyze a custom/analog block and generate a power grid view. She showed how this view can be brought into EPS for a full-chip analysis.
For more details, you'll need to view the webinar yourself. It's available free to members of the Cadence Community - quick and easy signup if you're not. You can see a list of all archived Cadence webinars here.