Chuck Cruse, team lead for emulation and FPGA-based prototyping at LSI Corp., wants to build a "deterministic" flow including virtual platforms, emulation, and hardware prototypes. In a recorded audio presentation at the Cadence web site, he describes the challenges he's experienced and what he hopes to see.
Cruse gave one of 30-plus customer and partner presentations at the EDA360 Theater in the Cadence booth at the Design Automation Conference (DAC 2012). These hands-on, interactive, 10-30 minute presentations covered a variety of IC and system design topics. Audio recordings and slides from most of the presentations are located here, and a previous blog post lists the titles of available presentations.
A key message in the Cruse presentation is that one size does not fit all. He noted that "emulation is very good for starting up your design and getting early RTL going, but ultimately you want a hardware prototype to match the real world environment as closely as you can." An FPGA-based prototype, he said, is a good hardware/software integration vehicle, and it can find problems that cross clock domains.
However, FPGA-based prototypes have some challenges. Getting the FPGA going is "kind of difficult, especially with early RTL." Visibility of internal signals is not as good as designers would like. Incremental changes need to be faster. With the Cadence Rapid Prototyping Platform, Cruse said, "our hope is that we can dump things into Palladium quickly and get it down into the FPGA and do hardware prototyping much faster than we could in the past."
What LSI would really like to do, Cruse said, is start out with SystemC models and then leverage those models in emulation and FPGA-based prototyping. LSI engineers are hoping to do hardware/software integration in a virtual platform before writing RTL or running emulation. This will help avoid the "step function" or "big bang" that occurs when hardware and software are brought together later in the process, and don't want to play together.
In the presentation, Cruse describes how LSI envisions this "SystemC to FPGA" flow will work, and he shows how the Accellera SCE-MI standard can make it possible. "We really like it that standards are starting to evolve," he said.
There's a lot packed into this 10-minute presentation. To view it, click here.
Separately, Cruse was a panelist at a Cadence-sponsored DAC breakfast on hardware/software co-development. A blog report on that breakfast is located here.