The IC physical design team at Marvell Technology Group Ltd. has a tough challenge. They're under a lot of pressure to minimize power consumption as much as possible, while getting products out the door quickly. In a recorded presentation at the Cadence web site, Murali Natarajan, senior physical design manager at Marvell, talks about low-power design challenges and the solutions that Marvell has found.
The presentation, titled "Accelerating Advanced Low-Power Implementation Using Common Power Format," was one of 30-plus customer and partner presentations at the EDA360 Theater in the Cadence booth at the Design Automation Conference (DAC 2012). Audio recordings and slides from most of the presentations are located here, and a previous blog post lists the titles of the available presentations.
In his presentation, Natarajan noted that Marvell designers are increasingly using low power technologies such as power shutoff, dynamic voltage and frequency scaling (DVFS), and retention logic. Typical low-power designs have 5 or more power domains and 20-30 operational power modes. Dual-rail memories operate in full power, partial power, or shutoff modes. Designs include isolation cells, level shifters, retention cells, and disjoint power domains with multiple modules in each power domain.
Often, Natarajan said, Marvell designers "convert" existing designs into low-power designs by adding multiple power domains. And here's the problem - a lot of timing paths may cross those domains. "The logical crossing between the power domains is rarely controlled, which means that you can have lots of nets crossing from one power domain to another," he said. "That demands that isolation cells and level shifters are inserted at the right nodes, and that can sometimes be very tricky."
Having a single power intent file format - in this case, the Common Power Format (CPF) - for both implementation and verification is a big help, Natarajan said. He cited these advantages for CPF:
Marvell uses the Cadence RTL Compiler to insert low-power elements. It provides "out of the box power intent integrity," Natarajan said. "What I mean by this is that the tool inserts isolation cells and level shifters at the correct node, making it easier for timing closure. Also the tool does not insert redundant isolation cells, and scan insertion is low-power aware." He noted that designers rely on the tool to optimize cross-domain nets.
Marvell also uses the Cadence Encounter Digital Implementation System. Natarajan said the tool is constantly aware of power integrity, handles power connections for newly added cells, calls Conformal Low Power to verify power intent, and doesn't have significant run-time or memory overhead for low-power designs.
"At the end of the day, we were able to achieve significant power savings and design time acceleration because of the way we were using the tools," Natarajan said. You can listen to his 10-minute presentation and see the slides here.