By leveraging Common Power Format (CPF) constructs and removing some older Unified Power Format (UPF) commands, the emerging IEEE 1801-2013 standard (UPF 2.1) will help enable "methodology convergence" with CPF. Kamran Haqqani, principal engineer at Maxim Integrated, will be happy to see this convergence - and he wants to see better mixed-signal solutions.
Fellow Cadence blogger Adam Sherer and I recently spoke with Haqqani, who works in the EDA Group at Maxim and focuses on functional verification. He deploys verification tools and low-power methodologies in mixed-signal environments for multiple business units across Maxim. He takes a very hands-on approach, writing CPF himself and running tools like Cadence Conformal Low Power (Conformal LP).
I asked Haqqani what his biggest low-power verification challenge is, and he immediately said that "at Maxim everything is mixed-signal and analog." So far, CPF has been employed only for digital verification, and digital design is in fact increasing substantially at Maxim. But part of Haqqani's charter is to extend the CPF flow and other aspects of "digital" low-power verification into the mixed-signal world.
Analog is Different
Compared to digital, "analog is very different," Haqqani noted. "Analog designers start off by hand designing things in a schematic environment. If proper partitioning is not put in place, low power cells can be hidden all over the chip, and you need to make them visible so verification tools can verify them." Maxim's low-power verification flow includes dynamic, static, formal, and transistor-level checking tools.
Haqqani noted that multi-voltage techniques are very commonly used for mixed-signal designs, and the number of domains is increasing. Many projects are moving towards power gating techniques with retention, and dynamic voltage and frequency scaling (DVFS). These are primarily digital techniques, but Maxim is looking at methodologies for applying power shutoff and DVFS and other power reduction techniques to mixed-signal designs.
CPF and UPF
Haqqani said he is "very aware" of both CPF and UPF and how they are used, and he has been watching the IEEE 1801 standardization effort closely. He said that Maxim has a mix of both formats, but primarily uses CPF. "Both CPF and UPF have their own unique advantages," he said. "There are certain things in CPF that favor the mixed-signal side of things, and we want to keep taking advantage of those capabilities." One example is the ability of the Cadence Virtuoso platform to automatically generate CPF macros for analog blocks.
"If you stick to one language there are fewer issues and challenges," Haqqani said. But UPF has its advantages as well, he noted. For example, it requires less work to come up with technology information for simpler power management library cells. For more complex cells, however, Maxim uses CPF's macro model capability.
Haqqani thinks power format convergence is a great idea - in fact, he wishes it had happened sooner. "I definitely think the industry is moving in the right direction for digital flows," he said, but when it comes to mixed-signal, "I still see a lot of work that has to be done." He is happy that the CPF macro capability made it into the new IEEE 1801-2013 standard, but said that "it's still somewhat restricted to a gray box view." Haqqani would like to see a solution that makes it easier for simulation to provide power estimations for those macros.
Recommendation to CPF Users
With CPF, Haqqani noted, Maxim is already using most (if not all) of the capabilities that the new revision of UPF will bring. But if there is some additional capability for mixed-signal verification, Maxim will look at it very closely, he said.
"We are looking forward to the new [UPF] standard," he said, "but we are not recommending that people jump in right away. We will be watching it, reviewing it, and validating it as the constructs become available through the tools. We will wait until the dust settles and the tools support the new constructs well and all ambiguities are removed." Also needed, he noted, is back-end tool support.
Looking towards the future, Haqqani said, "more work needs to be done with things like mixed-signal assertions and coverage closure. You should be able to capture all these and connect to your verification plan. Some of the pieces are already here, but I think there are still things that can be improved. We would like to see more capabilities for mixed-signal design."
Related Blog Posts
Q&A: Qi Wang Updates EDA Power Intent Format Standards
Engineer Video: Best Practices for Mixed-Signal SoC (MS-SoC) Verification
New Incisive Low-Power Verification for CPF and IEEE 1801 / UPF