Emulation provides blazing fast verification speeds, but you still need a good methodology to get the most value from it. At a recorded Cadence Theater presentation at the 2013 Design Automation Conference (DAC), Mehran Ramezani, senior manager for firmware at Broadcom's Mobile and Wireless Group, showed how his company is speeding system bring-up with an "embedded testbench" methodology using the Cadence Palladium emulator.
Ramezani began his talk by noting that system-on-chip (SoC) functionality is increasing while the time available to design SoCs is decreasing. Broadcom, for instance, has an SoC baseband for cell phones that packs more functionality into a square centimeter than you find on a PC. Meanwhile, from April 2010 to March 2011, over 110 new smartphones were introduced by the top six manufacturers. "This shows the lifecycle of the cell phone is shortening, and if we don't do much about the development and verification of these SoCs we will not be able to sustain this trend," he noted.
Ramezani identified the following firmware and hardware pre-silicon development challenges:
The Case for Emulation
A baseband SoC, Ramezani noted, cannot be fully tested without its peripherals. The actual system, however, is not available until post-silicon. Hardware/software co-debug is difficult, if not impossible, on actual silicon. "We need something to debug and verify systems before they become silicon," he said.
FPGA development systems are "great" and "fast," Ramezani said, but it is impossible to fit a complex SoC into one FPGA. Thus, users must partition a portion of the SoC design into several FPGA devices. FPGA development systems can't run peripherals at speed, have a limited number of clocks, and may not fully represent the actual design.
With emulation, however, "we can fit practically every bit of that cell phone [SoC] into the Palladium, except we cannot pick up the Palladium and make a phone call." Broadcom engineers use a fully synthesizable, cycle-accurate embedded testbench that maintains data transfer speeds between the SoC and its peripherals, and provides good visibility for debugging complex scenarios. Automated assembly software makes it easy to reconfigure the SoC and its peripherals.
The presentation provided more detail about how the embedded testbench approach works. Basically, synthesizable bus-functional models are used for standard interfaces, and firmware-controlled peripheral models behave like the actual device. The embedded testbench can be used with other modeling technologies, such as Cadence SpeedBridge adapters for peripheral devices.
With the Palladium emulator, Ramezani noted, Broadcom engineers can develop device drivers ahead of the silicon, debug the software that is supposed to be ready when the silicon arrives, measure performance, find any problems in the RTL, and enjoy "enormous" visibility into the SoC. "We can find out why performance was not achieved and what is blocking the traffic," Ramezani said. "And we can do that for every node and every signal inside the SoC. This is very valuable."
So why Cadence? One reason is that Cadence offers a "full verification solution" with its System Development Suite. That suite includes the Palladium XP Verification Computing Platform, which Ramezani said "has been invaluable for us." He noted that the Palladium XP platform is very high capacity, supporting up to two billion gates in a modular architecture. He observed that Broadcom has substantially increased its usage of the Palladium solution over the past 12 months.
"Just recently an SoC came back after being fabbed, and in a matter of hours our software was running on it," Ramezani said. "This would not have been possible if the software was not debugged on an emulation device. And we had all the software and device drivers ready by the time the ASIC came." Result: Broadcom's fastest SoC bring-up ever for a new architecture on a complicated chip.
An audio recording of this presentation, along with slides, is available at http://www.cadence.com/dac2013/Pages/theater.aspx. You'll find it listed as the Monday (June 3) presentation at 2:30 p.m.