First, the bad news. We may have to go all the way to the 7nm process node without extreme ultraviolet (EUV) lithography, using increasingly clever tricks—and design restrictions and constraints—so our current generation of 193nm lithography tools can print features correctly on silicon wafers.
But there may be a silver lining. According to Lars Liebmann (right), distinguished engineer at IBM and a keynote speaker at the International Conference on CAD (ICCAD) on Nov. 19, 2013, restrictions and constraints may open up new design methodologies. His talk was titled "The Escalating Design Impact of Resolution-Challenged Lithography."
While Liebmann is a renowned lithography expert, ICCAD is primarily a conference for EDA developers. Liebmann said he had come to ICCAD to "share with you a little bit of how far we're bending over backwards to keep [semiconductor] technology moving forward." He cited a growing need for deep and early collaboration among designers, EDA developers, process engineers, and lithography experts, and noted the need to "mutually understand what problems we're trying to solve."
Liebmann cited these goals for his fast-moving, technically deep, hour-long keynote:
"In the good old days, you had an infinite variety in the length and width of transistors, and now we're down to maybe one or two channel lengths and a 2-fin or 3-fin device," he said. "But maybe there's some opportunity to improve how you approach design and not just treat it as a restriction."
Some basics about lithography
When considering lithography issues, Liebmann doesn't pay too much attention to technology node names such as 22nm or 10nm, noting that these node names "have nothing to do with any kind of physical dimension in the technology." What's more important is the minimum pitch that has to be resolved. At the 22nm process node, that's 80nm. At the 14nm process node, that's 64nm. This is an important distinction because double patterning is generally required below an 80nm minimum pitch.
But the main variable Liebmann watches is the Rayleigh Factor, abbreviated as k1. This is basically a measurement of how complex the resolution is—the lower the number, as Liebmann put it, "the harder your lithography team is working." Yield, cost, and complexity all become problematic when k1 = <0.65.
When IC process nodes shrank lower than the 193nm wavelength provided by steppers, lithographers employed "tricks" to keep printing features accurately on silicon. One technique was optical proximity correction (OPC). Here, Liebmann said, "we would basically build mathematical models of how features are distorted on the wafer as a function of diffraction efforts. We would effectively pre-distort the mask by taking layouts and adding distortions or decorations so we could get an image that more closely resembled what the designer had in mind."
Just as the invention of the airplane was followed by the invention of the parachute, Liebmann said, OPC was quickly followed by "lithography-friendly design" in case OPC didn't quite work out. The idea here was to provide models to designers rather than presenting hundreds of restrictive design rules. Following a lithography simulation, designers could fix "hot spots" to eliminate problematic layout configurations. OPC and lithography friendly design reduced the k1 factor to 0.5.
Going off the axis
The next lithography trick, off-axis illumination, is pretty much what it sounds like. If you can tilt the illuminator on its side at exactly the right angle, Liebmann said, you can form an image that prints correctly on silicon. In addition, you can double the resolution and get close to k1=0.25.
But from a design perspective, there's a downside. "Going off axis was a genius move, but then we had to deal with non-monotonic behavior and design rules became incredibly complicated," Liebmann said. Still, he said, the industry got past three technology nodes with that technology. Around the same time equipment manufacturers started providing immersion lithography, accomplished by placing a layer of water between the lens and the wafer.
Another bag of tricks came with asymmetric illumination techniques such as double dipole lithography (DDL) and source mask optimization (SMO). These techniques involve very sophisticated optimizations that require collaboration between lithography teams and designers, who may have to design everything in one orientation (vertical or horizontal). The resulting features "are not pristine but are within spec, and you can avoid multiple exposures."
If you're doing SMO, Liebmann noted, you can get a 15% improvement in pattern variability by reducing the number of layout constructs and doing a detailed optimization. "Let's not argue over design rules," he said. "Let's argue over what are the exact shapes you need to build your design, and how we can design tools that think in terms of constructs rather than rules."
Lithography for 14nm and below
If you want to go below k1=0.25, it will have to be done with double and/or triple patterning. With the simplest approach to double pattering, litho-etch litho-etch (LELE), you are simply printing half the patterns at twice the pitch. This works when the minimum pitch is between 50nm and 80nm. At the 10nm process node, however, when the minimum pitch is below 50nm, self-aligned double patterning (SADP, also called sidewall image transfer) is needed. Rather than a detailed explanation here, I'll just note that this is a much more complicated process that involves forming relief features called "mandrels," depositing sidewalls, and cutting away patterns that are not needed.
With the "first generation" of multiple patterning (14nm process node), Liebmann said, only a few metal levels need LELE. In the "second generation" (10nm process node) more levels will need LELE, a few levels will use SADP, and a few levels will need triple patterning. Why triple patterning? "We need the third color to overcome 2D violations," Liebmann said.
What about design? Liebmann emphasized that the entire IC physical design flow needs to be double-patterning aware. He presented some of the requirements for placement, routing, and extraction. For routing, he noted, it's not enough to follow the relatively simple set of LELE rules—routers must also be ready for SADP, which will impose limitations such as forbidden spaces. Liebmann said researchers came across some unexpected challenges with line-end stagger rules and via coloring.
Liebmann briefly mentioned some work he has been doing with Cadence on via coloring, line-end stagger rules, and cell flipping and color swapping. "If you want to get into this game, you have to start early," he said.
What happens if EUV isn't ready?
For many years, chip makers have awaited the commercialization of extreme ultraviolet (EUV) lithography. It has many advantages, including a 13.5nm wavelength (compared to 193nm for optical lithography). It has many challenges, including source power, image placement, and mask defects. IBM hopes to run some integrated wafers using EUV next year, but Liebmann noted that "there is still a huge possibility that this [EUV] won't be ready for 7nm and we will have to keep going with other means."
What other means? One may be block copolymer directed self-assembly (DSA). This is a material-based method that extends the patterning capability of 193nm steppers. "We take every fourth space and make it a guide pattern," Liebmann said. "We apply a copolymer film, heat the thing up, and like magic that film self-assembles into the pitches we need in our design."
Another possible approach is to take SADP and turn it into SAQP—self-aligned quadruple patterning. It's easier to understand than DSA, but it requires even more mask layers than SADP.
"The significant outcome of all this work," Liebmann concluded, "is that once you deal with the fact that your layout is very constrained, you can take advantage of it and come up with a very optimized design environment where everything is synthesized, you no longer have custom layout, and you have smart memory compilers. You can get significant improvements in design efficiency."
This ICCAD keynote session was organized by Joel Phillips, senior architect at Cadence, on behalf of the IEEE Council on EDA (CEDA).
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