Functional verification costs are skyrocketing at 40nm and below, and the only solution is to dramatically increase verification productivity. Cadence this week (Feb. 24, 2014) is responding with the Incisive vManager solution, an all-new verification planning and management environment built on a client-server architecture and an SQL database.
At this point you may be saying, "I've been using vManager for years" or "I've heard of vManager before." That was, in fact, the original name of a product introduced by Verisity before Cadence acquired the company in 2005. Cadence renamed the product "Incisive Enterprise Manager," and for eight years now it has been helping users run regression suites and analyze results using a metric-driven verification (MDV) methodology (right). The new Incisive vManager does that too, but it has capabilities that go far beyond the Incisive Enterprise Manager.
"We are introducing a brand new solution that is going to revolutionize verification planning and management," said John Brennan, product marketing director at Cadence. That's a bold statement, but it's based on some important new capabilities in Incisive vManager, including the following:
The diagram below provides a closer look at the new Incisive vManager solution. Four "activity centers" are at the top of the diagram. The Planning Center allows users to build executable verification plans (vPlans). The Regression Center lets users submit jobs to the compute farm. The Analysis Center shows whether features in the design have been covered or not. The new Tracking Center makes it possible to see whether a project is progressing properly. Again, it's all built upon a client/server architecture and an SQL database.
So what is driving demand for this kind of solution? Brennan cited three top-level business concerns. One is the age-old question of when verification is done. Another is the high cost to tapeout with any chip at 40nm or below, with verification costs increasing faster than the cost of design itself. A third concern is that a functional bug may force a re-spin, or in worst case a recall, if the bug is not found in time.
Brennan said that Incisive vManager helps alleviate these concerns by providing schedule predictability, verification productivity, and improved quality. Most projects, he said, have up to a 50% uncertainty about verification completion. But vManager "provides exact details to determine exactly where you are, feature by feature, inside your chip."
Verification productivity is enhanced by a GUI that lets you see where the problems are, so you can shift resources if needed and get back to your schedule. Incisive vManager also optimizes testing on compute farms, and supports formal engines and acceleration. Finally, vManager provides increased quality because the more metrics you use, the more complete the testing.
Brennan said that vManager "allows you to easily see where the most critical failures in the design are, so you're not wasting cycles continuing to test things that are not really in a problem area." Users can work on the most critical failures, shift verification resources as needed, eliminate redundant cycles, and fill coverage holes.
Early customers have reported the following results:
In short, Brennan said, the use of Incisive vManager with a metric-driven verification methodology can result in a 2X improvement in verification productivity. And that improvement will be very welcome for the gigascale IC designs that are right around the corner.
Further information, including a white paper and a data sheet, is available on this landing page.
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