Whoever said "there is no such thing as a free lunch" has not been to the Design Automation Conference (DAC 2014). This year at DAC, Cadence is sponsoring one breakfast and three luncheons that will include presentations or panels on four emerging challenges - mixed-signal power management, software-driven verification, cross-fabric interface design, and high-performance digital design for the enterprise datacenter.
DAC 2014 runs June 1- 5 in San Francisco, California. The Cadence breakfast and luncheons will be held in room 104 at the Moscone Convention Center, located in front of Exhibit Hall B. Space for the breakfast and the lunches is limited, so register now for any of the following events.
Timing signoff panel at Cadence DAC 2013 lunch
Monday, June 2Lunch: Extending Mixed-Signal Power Management Verification to RTL12:00 - 1:00 pm
Mixed-signal power management and verification are posing serious challenges for IC development. Come and learn how your colleagues are dealing with these growing verification challenges, and how new methodologies and techniques can keep you a step ahead of tapeout failure nightmares. Panel includes experts from Maxim, Broadcom, NXP and Cadence.
Tuesday, June 3Breakfast: The Shift to Software-Driven Verification8:00 - 9:30 am
The development, integration, and verification of complex hardware/software systems is demanding a "shift left" in which tasks traditionally done post-silicon must be done much earlier. Speakers from companies including AMD, Microsoft, and Cadence will note how software has become an important part of the verification process, and will discuss challenges that designers are facing.
Tuesday, June 3Lunch: High-Speed Cross-Fabric Interface Design: It's not 1's and 0's Anymore, It's a Noisy World12:00 - 1:00 pm
Cross-fabric analysis (chip-package-board) is a necessity for high-speed digital design. Design practices will have to shift to co-design and in-design techniques to solve closure issues. At this session, a panel of experts from Altera, Cisco, Intel and Cadence will share their experiences and their thoughts about what's needed for high-speed digital design.
Wednesday, June 4Lunch: How High-Performance Digital Design Enables a Paradigm Shift in the Enterprise Datacenter12:00 - 1:00pm
Next-generation, 64-bit server architecture-based SoCs represent an exciting inflection point in the networking and cloud computing industry. Panelists will discuss what is taking place in the industry to help 64-bit technology deliver high performance at higher efficiency than traditional processor offerings.
Interested? To learn more about these events, and to register, click here.
For a complete overview of Cadence DAC 2014 activities, click here.
See you in San Francisco!
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