Take it from the people who do it for a living—mixed-signal IC verification is fraught with challenges that can cause tapeout delays or failures. But there are tools and methodologies that can help, according to panelists at a Cadence-sponsored luncheon at the Design Automation Conference (DAC 2014) on June 2.
The panel was moderated by Brian Fuller, editor in chief at Cadence. Participants were as follows, shown left to right in the photo below:
"You've got yourself some serious challenges," Fuller said at the opening of the panel. "In mixed-signal design, you can have thousands of connections between digital and analog blocks. How can you verify things like DSP, timing, and power isolation? How can analog and digital designers speak the same language?"
Here's what the panelists had to say with their opening statements.
Rael—Digital verification challenges without the tools
Rael noted that Broadcom develops radio IP that is used in wireless LAN, Bluetooth, cellular, near-field communication (NFC), and microwave back-haul applications. The IP ranges from 10MHz to 80GHz. Because of requirements for very high yields, low power dissipation, and programmable power/performance tradeoffs, there is lots of digital control logic.
"Radio designers end up with the same challenges as digital designers, but we don't have digital tools to solve problems," Rael noted. Typically the digital designers will place all the digital functionality in one block and expect the mixed-signal designers to connect all the wires. That makes it hard to close timing, he said. Because the layout for the radio block is handcrafted, engineers can't get accurate parasitic information for that block until they're just about ready to tape the chip out.
Haqqani—Extending digital verification concepts
Maxim provides analog/mixed-signal chips for many manufacturers and applications. Demand for highly integrated analog systems has sharply risen, and with it come severe challenges on the verification side. To overcome mixed-signal verification challenges, Maxim has extended digital verification concepts into the analog world. These include:
Verifying low power is especially challenging, Haqqani said. "We had to go back to some of the fundamentals," he said. "What needs to be verified dynamically, what needs to be verified statically? The problem is still ongoing and there's a lot to be done."
Nazifi—An EDA vendor viewpoint
Echoing a point made by Rael, Nazifi noted that increasing amount of digital content in analog/mixed-signal blocks. One reason is that analog doesn't scale well, so digital content is needed to achieve performance and minimize area.
"When you bring in more digital content, you're introducing additional challenges with regards to verification and implementation," Nazifi said. "With power management, a lot of complexity comes into play because you have multiple Vdds and techniques such as power shutoff."
From a tool-development perspective, Nazifi said, Cadence is focusing on addressing power-management verification challenges. This includes "enabling what we call power-aware dynamic verification, so your mixed-signal simulation can actually be power aware." Meanwhile, Cadence supports real-number modeling, a technique in which real numbers (such as 1.2 volts) can be used in event-driven simulation.
Questions and answers
Q: What problem would you most want to have solved a year from now?
Rael: The timing closure problem I described earlier is the biggest problem. We still haven't found a good solution for that, and we are working with Cadence to try and solve it.
Haqqani: We have power management cells that need to be verified. We need a good connecting mechanism to be able to verify those [cells] within the context of UPF and CPF. This is something we are working on with Cadence.
Nazifi: One of the biggest challenges we run into, from a management perspective, is ownership—who owns this [verification] problem? Is it the analog IP design team, the verification team, the SoC team, or somewhere in between?
Q: Koorosh, what's in the wings at Cadence to address these challenges?
Nazifi: We are focusing on the verification challenges of the analog/digital interface, both from a timing perspective and a power management perspective. We are also focusing on modeling automation. If you have an analog block that has digital cells, timing model creation becomes significantly more challenging.
Another area has to do with handoff—making sure you always have the right representation for your IP, so when you hand it off to the SoC team, they have all the information they need to integrate that IP. Finally, we're creating automation that allows analog designers to pass along top-level integration constraints to the SoC team.
Q: What's the format for the information that needs to be specified and passed along?
Nazifi: It's OpenAccess, which is an open format. Basically we are relying on OpenAccess to capture and store the necessary information, then have the subsequent tool—in this case [Cadence] Encounter—open it up and read the information.
The Cadence mixed-signal strategy links Virtuoso custom/analog design and Encounter digital design with the OpenAccess database.
Q: Are you primarily relying on CPF [Common Power Format] and UPF [Unified Power Format] for low-power verification?
Haqqani: We have a non-CPF-based verification method. However, we are using CPF and as the convergence [with UPF] happens, we will use more of it. CPF lets us keep the design intent in one place. There are certain things in CPF that are a little bit ahead of UPF.
Rael: Customers are starting to request a UPF model, and we don't have a tool that will generate it very easily. At this point we give them some data and they write their own UPF model. In the long term, we're going to have to generate a UPF file.
Nazifi: CPF and UPF are formats that introduce power management for digital designs. But digital doesn't exist by itself—analog is always present. We acknowledge this by introducing certain constructs so you can specify analog pins on an IP block, and our tools will not touch those pins. The next level of challenge has to do with voltage—what if this analog IP offers a different voltage level? A third level will give us something that dynamically models voltage.
We are looking at what can be done. The first phase is to enhance tool capabilities. Language extensions are further out.
Q: I want to run a full-chip simulation with an analog block in a SPICE netlist. Is there any solution for that?
Rael: You can use RTL models for the digital while running the analog on high accuracy. Cadence has a good mixed-signal simulator that will automatically insert connectors that translate a 0 or a 1 to an appropriate voltage level to drive the analog blocks.
Nazifi: Another possibility is to use real number modeling. It's a way of representing the electrical behavior of analog IP, but using an event-driven simulation as opposed to running an analog solver.
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