FPGA-based prototypes provide excellent platforms for pre-silicon software development - but prototype bring-up times are so long and painful that much of the value is lost. Promising to shorten bring-up times by up to 70% versus competing commercial and "roll your own" in-house solutions, Cadence today (July 17, 2014) is announcing the Protium platform (shown at right), its second-generation FPGA-based rapid prototyping solution.
Compared to the first-generation Rapid Prototyping Platform (RPP), Protium offers 4X the capacity (up to 100M gates) and 3X the memory. Protium also provides a 5X compile time improvement using Palladium and Xilinx verification and design flows. The new offering can reuse 80% of the existing Palladium environment. Protium runs up to 5MHz in a fully automated regression mode, and tops 100MHz in a "black boxing" mode inside a single FPGA.
This week Cadence is also announcing IEEE 1801 (Unified Power Format, UPF) support for the Palladium XP II verification computing platform. Like the Incisive simulation environment, Palladium XP now supports both UPF and the Common Power Format (CPF). This provides a more consistent verification flow across the Incisive and Palladium platforms, and it complements the Dynamic Power Analysis capability in Palladium.
A Broader Picture
The Protium and Palladium XP platforms are part of the System Development Suite, which provides a set of connected hardware/software development platforms for virtual prototyping, simulation, emulation, and FPGA-based prototyping. The Protium platform is typically employed after RTL coding is complete. It runs faster than Palladium emulation, but does not have all the debug capabilities of emulation. Users can find bugs quickly with the Protium platform and then run a thorough debug analysis on the Palladium XP platform.
The Protium platform supports several use models. One is pre-silicon software development. Another is automated throughput regressions that are targeted for the project phase in which RTL starts maturing, fewer hardware bugs are found, and users want to run more verification cycles that do not require all the capabilities of emulation. Besides software development and throughput regressions, the Protium platform is also a suitable solution for system validation - making sure that the hardware/software design executes within its system environment as intended.
The big problem with FPGA-based prototyping is bring-up time - that is, everything that it takes to compile an ASIC design into multiple placed, routed, and verified FPGAs that fully represent system functionality. "It is very important to bring up your prototype very quickly, because every week takes time away from when you can really use it," said Juergen Jaeger, senior product manager at Cadence. "Our goal is to shorten the bring-up time for FPGA prototypes from months to weeks."
Compatibility with Palladium Platform
The following diagram shows how the Protium platform works within a Palladium-compatible flow. This flow provides fast prototype bring-up with a golden pre-partition model and a post-partition verification model. Design migration is made easy with identical language coverage, common setup files, identical defaults, reuse of script files, identical clock handling, and SpeedBridge compatibility.
"For designs that have run in Palladium, we're seeing bring-up times in days. Before it might have been four or five weeks," Jaeger said.
Protium offers a number of improvements compared to the previous generation solution. One is a new fast partitioning capability that uses the Palladium partitioner, making design migration between the Palladium and Protium platforms easier. The Protium platform can compile and partition up to 75M gates/hour on a single workstation.
The Protium platform boosts capacity by using Xilinx Virtex-7 FPGAs. Users can have either two or four FPGAs on a board, and up to two boards per chassis, providing up to eight FPGAs with around 100M gate capacity. I/O connections include two 150-pin daughtercard connectors per FPGA.
One important Protium feature is automatic, emulation-like clock tree transformation. "We completely analyze design and convert multi-clock domain designs into single clock domain designs," Jaeger explained. "We are eliminating things like gated clocks, multiplexed clocks, latches, and tri-states, all of which are structures that cannot map directly into FPGAs." The Protium platform can also support an unlimited number of design clocks, remove FPGA hold-time violations, and reduce the complexity of clock trees in order to speed placement and routing.
The Protium platform also uses high-performance LVDS (low voltage differential signaling) pin multiplexing. The compiler automatically determines if a single-ended wire or LVDS (which runs the same signal over two wires) results in faster performance.
Choice of Performance Modes
The Protium platform offers three performance modes. A fully automatic mode, which provides ASIC memory mapping, partitioning, and FPGA placement and routing, runs 5-10MHz. A manual guidance mode takes partitioning input and runs 20-50MHz. A "black boxing" mode uses a single FPGA device and runs over 100MHz.
The Protium platform supports two approaches for modeling memories. In the automated regression mode, users can plug in an XDRAM card and draw from a large memory model portfolio. This approach offers fully automatic memory compilation. In the manual guidance and black-boxing modes, users take advantage of directly connected bulk memories. Some manual work is required, but the result is higher performance compared to the fully automated approach.
Finally, although the Palladium platform will always have superior debug capabilities compared to any FPGA-based prototyping solution, the Protium platform offers debug features such as real-time signal monitoring, force/release signal, internal memory upload and download, probes (runtime data capture), waveforms across partitions, and a start/stop runtime clock capability.
Further information about the Protium rapid prototyping platform is available at this landing page.
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