3D NAND Flash architectures will provide the best option for increasing storage densities in future years, according to panelists at a plenary session at the Flash Memory Summit Aug. 5, 2014. But given the large manufacturing investment required, and concerns about reliability and yield, 3D NAND is not a viable solution yet, panelists said.
The session was titled "Is 3D NAND a Disruptive Technology for Flash Storage?" It was moderated by Jim Handy (below, far right), chief analyst at Objective Analysis. Panelists were as follows, shown left to right in this order:
The Flash Memory Summit ran a plenary panel on the same topic in 2013 (see blog report here), and in my view the 2013 presentation had a more optimistic tone. Last year we heard that manufacturing costs for 3D NAND will be lower than they would be if we simply extended existing planar NAND, and that challenges were mostly under control. This year was more about challenges and limitations, and there was a stronger sense that 3D NAND is not ready yet.
Micron's Kilbuck said it succinctly. "You'll get the best cost, reliability, and performance tradeoffs by staying on planar NAND for at least the next couple of years," he said. "Don't pay an early adopter premium." But speaking of Micron and other NAND Flash suppliers, he also said "now we're all going to do it [3D NAND] and we're all going to eventually invest enough money to realize it - it's just a huge investment to do that today."
Panelists first gave 10-minute presentations, with some of the main points summarized below.
Er-Xuan Ping - Manufacturing View
Ping said that 3D NAND is definitely a disruptive technology, because the devices are significantly different from traditional NAND. He said that 3D NAND devices use charge trap storage and allow better gate control. "This is why a device can provide a path to low power, high reliability, and high density," he said.
However, 3D NAND Flash has a lot of challenges. Here are some that Ping noted:
"My message is that processing is challenging and different," Ping concluded. "The scaling path is different. There will be a lot of consideration for both vertical and lateral dimensions."
Kevin Kilbuck - "Not There Yet"
"Yes, 3D NAND is disruptive technology - it's just not there today," Kilbuck said. "The economics for suppliers are not there yet. The benefits for users are not there yet."
Kilbuck observed that 3D NAND Flash offers the promise of getting back to Moore's Law scaling. Flash memory was actually beating Moore's Law up to about 3Xnm, and then flash hit some fundamental limits. Now flash has fallen behind what Moore's Law would predict for scaling.
Kilbuck said that 3D NAND Flash will become practical - and necessary - at 256Gbytes, especially for MLC (multi-layer cell) devices. "We don't think 256Gbyte MLC is possible with planar technology," he said. As for performance, he said that early indications are that the numbers "will be no worse than where we are today with planar NAND." Today's error management techniques can be used for 3D NAND, he added.
The problem for manufacturers, he said, is the cost of transition to 3D NAND. The cost is "almost off the chart," resulting in a capital expenditure that is "prohibitive for suppliers." Consequently, Kilbuck said, 16nm planar NAND is the best solution through at least 2015.
Handy added that cost per wafer is a big concern for NAND Flash manufacturers. "We've heard talk that the cost of going from planar to 3D NAND is similar to the cost of opening up a new fab," he said.
Erich Haratsch - Challenges Extend to Controllers
Haratsch said that planar NAND is running out of steam, and 1Znm will be the last node. This is because the cell size cannot be reduced much lower. 3D NAND makes it possible to relax the cell dimensions and capacity by adding more layers in the vertical direction. As such, he said, 3D NAND "appears to be the only viable option to increase densities for mass storage applications for the next 5-10 years."
3D NAND, Haratsch said, faces many of the same limitations of planar NAND - such as cell wear due to program/erase cycling, program disturb, and cell to cell coupling. 3D NAND also has some unique problems, such as coupling in the vertical direction, and yield challenges that arise because dozens of vertical layers may be grouped together.
How does 3D NAND impact controllers? That depends, he said, on the 3D NAND cell architecture and how different it is from planar NAND. It also depends on how program and read algorithms differ from planar NAND. Haratsch also said there will still be a need for LDPC (low density parity check) enabled controllers.
Hanan Weingarten - Scaling and Reliability Issues
Not everything is "hunky dory" with 3D NAND, Weingarten said. One problem is that designers can scale by adding layers, but there's a diminishing return in terms of cost. Weingarten showed a graph illustrating the relative bit cost per number of layers in a 3D NAND architecture. With two layers, the relative cost is half. But if you go from 32 layers to 64 layers, there is only a 15% improvement in cost.
Further, Weingarten said, adding more layers raises reliability concerns. With more transistors, he said, designers will see higher read disturbs and program disturbs. With TLC (triple level cell), he said, "reliability deteriorates quickly and you need to have modern decoding and encoding in place."
Beer and Pizza Finale
Cadence is a sponsor of the Flash Memory Conference, and immediately following the plenary session on 3D NAND, Cadence hosted a "Beer and Pizza with the Experts" event. Several dozen tables were set up, staffed by experts in such areas as software, standards, reliability, endurance, security, mobile applications, and more. As you can see from the photo at right, this was a very popular event and a great conclusion to a provocative plenary discussion.
Slides from the plenary panel presentation are available to conference attendees at the Flash Memory Summit web site.
Related Blog Post
Flash Memory Summit: What's Driving 3D NAND Flash, What Challenges Remain