As I’ve mentioned, I have done chip design for many years. And one thing I learned early was the concept of Golden RTL – the idea that the final chip netlist MUST match the final RTL.
Now, this can lead to certain anal-retentive behaviors. One rule we had was if we had to modify the RTL late, we had to re-run our verification suites. At a minimum I’d run those tests affected by the RTL, but ideally I’d re-run everything. This included changes made to the RTL that did not affect functionality, but were made to improve the ability to close timing. Say I restructured an if statement to move up a timing critical path or modified a pipeline to shift something around – I would expect that the tests would be fine, but I would still re-run everything. Then I’d use that Golden RTL as my reference design for all of my formal equivalent checks. This way, I’d know that my tapeout netlist was equivalent to my RTL, and I knew my RTL worked because I’d verified it.
Ok, let’s be really honest here – it drove my teams crazy, but I had a rule that if the date code had changed on an RTL file, simulations had to be re-run. So if someone did a touch on a file, I’d insist that it be re-verified. Even though the RTL had not changed at all. Obsessive compulsive, probably. But my chips worked.
So the question I have is: should power intent be treated the same way? Or should it just be a constraint, kind of like a synthesis script or timing constraints?
The advantage of making it be a constraint (like timing) is that each tool can write out what was done in that tool. So if the synthesis guy has specified a cell to be used for isolation, the output power constraint file will be modified to reflect that change. This gives the synthesis and P&R guys flexibility to make cell and power choices.
But in this scenario, what is going to check that the cell choice was correct and still implements the power intent correctly? Especially since power intent involves adding logic cells (isolation) to the design.
Note that I very carefully didn’t use the words, “CPF” or “UPF”. I’m really asking a flow question – either format can support having a Golden power intent.
So what do you think? What’s the right way to treat power intent? Treat it like a part of the design, keeping it Golden along with the RTL? Or treat it like a constraint?
Seems like anything that affects the functionality of the design should be treated like RTL. There are definitely power "constraints" that don't need to be treated this way - a max leakage constraint for instance, you can just catch that in a report. But anything like a shutdown domain, isolation or state retention affects the functionality and should be treated like RTL.
Good point about the max leakage/dynamic constraints – those clearly are constraints in the classic sense of the word. Since they manipulate the synthesis optimizations but don’t change the functionality, they really are a constraint on the optimization tool. And they’re not going to affect any Equivalency Checking that takes place – unlike the functional changes you mention.
Thanks for your comments,