These are follow up processors to their Shanghai core series. AMD has released both an energy efficient HE, and a high performance SE. These are AMD's entry into the quad core market, designed to compete directly with Intel's Xeon processor.
What I really found interesting was a mention of a new way of measuring power - Average CPU Power (ACP). The link to the white paper is: http://multicore.amd.com/resources/43761C_ACP_WP.pdf
Basically, ACP is measuring the power while running representative applications. The white paper specifically talks about the danger of looking only at peak power. From the story:
"It is of little value to measure power consumption by only looking at the spec sheets for different components, adding the totals together, because these generally only report the maximum power consumption. This scenario is like the car with a speedometer that tells you the maximum speed is 150MPH it's a maximum reading but it doesn't reflect daily usage."
This is the same problem many of my customers are also facing - how can they accurately determine the peak power of their chips while they can still impact the design? The old method of estimating switching activity just doesn't cut it. What I suspect really happens is that designers pad the estimate, leading to increased package and system cost.
"By utilizing ACP, customers can make a more educated estimate of their true power consumption. TDP, representing the thermal design power, is a rudimentary indicator of consumption, and may leave customers overestimating their data center infrastructure needs. In doing this, customers can potentially waste valuable data center space, resulting in un-optimized data centers that cost companies real dollars through their inefficiency."
AMD ran tests using a series of industry applications, and determined that the ACP reports are 23% to 34% less than the theoretical peak. So using this measurement can save a considerable amount of cost in building data centers.
Ok - that works for a server farm, but what about for a chip? How can you tell what is really running on a chip prior to tapeout, and how it affects power? Well, Cadence has had a solution for verifying actual operation for a long time - Palladium. And now we've enhanced it to perform Dynamic Power Analysis (DPA). This is up for EDN’s Innovation Award. The key thing is that this is not just counting activity - instead it is using RTL Compiler's power analysis capabilities to accurately capture the areas of peak power. Once identified, the design team can do something about it – maybe balance the load, maybe look at lowering the voltage. By having this knowledge before tapeout, the design team has been empowered to improve their chip's power profile (or ACP).
"AMD believes that ACP is a better way of thinking about typical CPU power that more accurately reflects the power consumption levels that customers can see in real life environments"
I couldn't agree more - measure the real power so you can take real actions.
ps: C-to-Silicon is also up for an EDN Innovation Award. I'll talk about ESL and power architecture selections in a future post.