Even though routing congestion sounds like a physical design
problem, it can cause chip projects to miss schedules, miss performance
targets, or result in a larger die size.
These are problems that are shared across the project, so if you want to
control the success of your chip design project, it is something to be
concerned about. But still, what can a
logic designer do about it?
Fortunately, today's physically-aware synthesis tools like
RTL Compiler can help relieve many congestion issues before they even show up
in physical design. More importantly,
you can use this technology to identify congestion issues up-front and quickly
triage the source of the problem. Maybe
it is something that can be fixed during synthesis, or maybe it is a floorplan
issue that the physical design team needs to address. There are no "magic bullets" because the
nature of the problem is so complex, but you can identify that there is an
issue up-front and figure out an action plan to address it before it affects
the project schedule's critical path.
Taking advantage of this requires some amount of
understanding of the types of problems that can occur, as well as methods for
addressing them. Fortunately, some of
our leading synthesis experts that are well-versed in physical design issues -
Matt Rardon, Ankush Sood, Mike Clarke, and Diego Hammerschlag - have put
together a nice white paper, Eliminating Routing Congestion Issues in Synthesis, that explains the issues and solutions as they
apply to logic design and synthesis.
Even a synthesis marketing guy could understand it!