Best Practices for Optimization
What should be my considerations while preparing data? Libraries, HDL, Constraints...
A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true for RTL Compiler. Before attempting to run synthesis, the user should check the input data, pay attention to the warning messages and correct any obvious issues.
How do I set and achieve my optimization goals?
There is no ‘one-size-fit-all' recipe for optimization; the recommended flow is to run the design through the baseline flow once with the ‘synthesize -to_map' command, analyze the result, then fine tune the flow if needed. So, how do I set and achieve my optimization goals?
Which approach is better?
Top-down vs. Bottom-up OR Wireload Model vs. PLE
To know more: Read Cadence Application Note on RC Optimization Best Practices
Fixing Timing Violations
How do I validate timing constraints? How do I analyze violating paths?
Let me guess some strategies for fixing violations... can the following tips help?
Creating different cost groups for I/O paths
Using multiple incremental synthesis and using path_adjust and changing datapath structure
Idealize high fanout nets and setting initial_target
To know more: Read Cadence Application Note on Tips for fixing the timing Violations in RC
Boundary Optimizations in RC
What are different types of boundary optimizations in RC?
How can I control it?
What are formal Verification considerations?
To know more: Read Cadence Application Note on Boundary Optimizations in RC
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