With shrinking design nodes, a significant portion of the delays are contributed by the wires rather than the cells. Traditional synthesis tools use fan-out-based wire-load models to provide wire delay information, which has led to significant differences in quality of results (QoR) between the "synthesis" and "implementation" tools. RTL Compiler Physical (RCP) as a tool allows the user to integrate the "physical" information much earlier in the flow, and this provides a good level of down-stream predictability that is superior to using wire-load models. Predictability will enable the designer to gauge very early in the flow how the design will perform after place and route. This, in turn, will help the designer reduce front-end to back-end hand-off iterations.
Yogesh Bansal and Aditi Bagree, from the Cadence TFO team, through their application note, "Physical Synthesis using RTL Compiler Achieving Best Quality-of-Silicon", talk about using "physical synthesis" aspects for design closure. The document is based on the 12.1 release of RTL Compiler, and captures the basic flow that needs to be followed. It also talks about the commonly faced problems and the possible resolution mechanism for the same.
Cadence R&D engineers and support and field teams are putting lots of efforts into developing similar self-help content for their tools and technologies, to enable their user communities to gain maximum productivity benefits of using Cadence solutions.
Recently, when I visited Cadence Online Support as an RTL Compiler user, I was pleased to know that the RTL Compiler team has developed several application notes to achieve the above stated objective. Here is an effort to compile the list of nine guides, collectively known as RTL Compiler Beginner's Guide, envisaged as the tool that will allow new users of RTL Compiler to do the first level of debug on their own. As a result, they can ramp-up extremely quickly, and can shorten turnaround times for their more mundane problems.
These individual application notes are intended to serve as a first point of reference for new users of RTL Compiler. The language adopted here is extremely simple, and adequate examples have also been included to ensure that the reader is able to relate to the philosophy of the tool and understand for himself or herself "how" and "why" a certain tool behavior is being observed. A conscious effort has been made to ensure that all the important aspects of the flow (DFT, LP, physical synthesis, etcs) are discussed in the separate app notes. This is to ensure increased readability, and that the reader is not overwhelmed by the amount of information presented in an individual app note. Apart from discussing flow-related aspects, certain best practices and good-to-use attributes are also documented. There's special emphasis on capturing the commonly used debug techniques in the app notes, too.
Following are the brief descriptions and links for all individual application notes:
RC Migration Guide
This document outlines the basic synthesis flow supported by RTL Compiler and is meant to help new users migrate from their existing flow to RTL Compiler effortlessly.
RC Logfile Diagnostic Guide
This application note helps new users of RTL Compiler to understand and diagnose issues from the RC log file. It lists common errors and their probable causes. This information can be very helpful in debugging common issues. The errors, commands, and debugging features being discussed here are based on the RC 11.2 release.
Design Navigation and Debug: The RC Way!
This application note explains the fundamental infrastructure available in RC for design debug. It talks in detail about the various commands and attributes that are used frequently to access design objects for the purpose of debug.
This document summarizes the usual practices and strategies that can be used in RC optimization. This also talks about certain latest features and the attributes of the tool that designers can use to refine their synthesis methodologies.
Low Power Implementation using RC
Today, almost every design undergoing synthesis has a requirement for low-power optimization. This document talks about the basic principles of low-power implementation in RC. The intent is to provide users with a simple methodology document that will allow them to understand the capabilities of the tool and help them in creating a basic framework for low-power implementation.
Design-for-Test Using RC
DFT insertion is an extremely important piece of methodology today. Moreover, it can have tremendous impact on the design closure activities as well, be it on QoR or the TAT. This document describes the basic set of commands and features that'll help the user to develop their DFT insertion methodology using RC.
Physical Synthesis Using RC: Achieving Best Quality-of-Silicon
This document talks about using "Physical Synthesis" aspects for design closure. The document is based on the 12.1 release of RC and captures the basic flow that needs to be followed. It also talks about the commonly faced problems and the possible resolution mechanism for the same.
RC Verification Guide
This guide provides a background in settings and designs that can impact the veriﬁcation of RTL Compiler synthesized netlists with Encounter Conformal LEC.
Advanced Low-Power Flow Using RC: Integrating CPF in the Flow
Advanced low-power techniques are becoming a routine affair while defining synthesis methodology. It is important for designers to understand the intricacies of different ways to define the power intent in RC. This guide covers the basics of CPF and some commonly used commands while implementing a CPF-based design in RC.
This above table may be updated in the future. The up-to-date table can always be found at RC Beginner's Guide
To access the complete application notes, please log in with your Cadence credentials at http://support.cadence.com
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