We have been talking about low power simulation and the Common Power
Format (CPF) for five or six years now. It’s become popular in most digital
designs thanks to a mature methodology and design flow. However, more and more
SoC designs are coming up with mixed-signal content. How will low power
technologies and formats be used in mixed-signal design?
For SoC design verification, we always involve an analog solver in our
simulation, no matter whether you are using Verilog-AMS to model your design
block, or changing a block configuration from the Verilog/VHDL level to its SPICE/Spectre
counterpart. When an analog solver is used, it can leverage the low power intent
expressed by CPF. Although CPF was defined for higher-level designs, it works with
analog solvers just as with digital content.
Fig. 1 CPF-AMS
In Fig.1 I drafted a simple diagram to show a scenario in which you
switch a module from the Verilog version to Verilog-AMS or SPICE (here it’s
ana_B). When you do this, there are three concerns:
the power intent described in CPF file is also available for the Verilog-AMS or
SPICE module. “Power domain” is a similar concept in both
digital or analog content. Whatever Verilog module or SPICE subcircuit that is
used to describe a circuit block should be handled in the same way for all low
power related properties with respect to CPF information.
the low power digital and analog modules are able to talk each other. Usually,
in mixed-signal simulation, a Connect Module is placed on the analog to digital
and digital to analog boundary. When CPF is specified in the design, the Connect
Module should have the capability to not only convert signal values from the logic
side to analog side, but also convert the correct CPF information from one
signal to the other.
In addition, where real number modeling (wreal) is used to represent
voltage or current instead of electrical signals, similar issues also will need
to be considered in wreal modules.