Getting a complex mixed-signal design assembled and completely analyzed for mask design is a huge challenge today. The IPs are complex and too many decisions need to be made to meet design budgets. All this is not possible with anything less than a fully automated, front-to-back mixed-signal design solution.
On top of mixed-signal complexity, battery operated wireless and hand-held mobile applications are extremely sensitive to power. Digital EDA tools bring the full force of the digital low power solution to mixed-signal designs. I can say that all the designs today are mixed-signal designs, and that mixed-signal implementation remains one of the biggest design challenges. A typical chip design today is a complete system with millions of gates that make up large numbers of DSPs, memories and processors, all of which must interface with the real world through displays, antennas, sensors and multiple communication channels. This requires integration of analog and digital content, without compromising performance or size, and on a technology scale that dramatically increases vulnerability to process and electrical variation.
Challenges to mixed-signal designs are real and are increasing. With process technologies moving to 32nm and below, the cost of design re-spins increases exponentially. Over 60 percent of design re-spins at 32nm and below are due to mixed-signal functionality, resulting in an additional cost and a delay in product rollout.
Designers require new implementation methodologies that will help solve these potential problems.
Currently, the majority of mixed-signal chip implementation planning is done by hand, which is a slow and laborious process that can lead to design errors and numerous iterations. During final assembly, the completed blocks are also placed and routed manually without the aid of DRC automation. Big analog designs with digital blocks traditionally start with schematic design, and then iterate through the floorplanning steps by manually placing the blocks according to design architecture, and assigning pins for blocks that could be analog as well as digital. Additionally, in the beginning of the design cycle, designers just have the top-chip floorplan and do not have much insight into the design implementation details.
Analog-on-Top (AoT) and Digital-on-Top (DoT) are block-based methodologies sufficient for many designs when functionality can be contained within the blocks with few analog-digital interfaces that are critical for design performance.
With OpenAccess as an integrated design database, many of those lossy format related design data translations can be avoided, and designers can use both analog and digital implementation platforms for achieving fast and more accurate results. Complete design analysis also becomes much more manageable and comprehensive with a full chip view including analog and digital blocks together within both physical implementation platforms.
Faster digital analysis methods such as static timing analysis, signal integrity analysis, and IR drop can be applied on mixed signal designs. One can get best of both full custom analog implementation environment in Virtuoso IC 6.1 and digital implementation in the Encounter Digital Implementation platform. Both IC 6.1 and Encounter Digital Implementation 9.1 read and write the OpenAccess database.
I invite further discussions to challenge, discuss and debate some of the possibilities that are opened by OpenAccess as an integrated design database.