According to Jag Bolaria of the Linley
Group, the 5 Gbps version of PCI Express has moved beyond PC applications into
embedded systems and networking. In his article in DesignLine, we learn that PCIe Gen2 channels are limited to about a length of 10 inches (without connectors or
Take a look:PCI Express goes everywhere
Are you running up against these sorts of constraints in your PCIe
2.0 designs? Have you looked into using
the Channel Analysis features in Allegro PCB SI GXL to validate your
channel design before prototyping?