Cadence has been a leader in silicon-package and package-board co-design for over a decade now. Today, Cadence introduced a new and innovative solution for FPGA-PCB Co-design.
The FPGA-PCB co-design solution includes proven technology from Taray Inc for optimized, correct-by-construction FPGA I/O pin assignment synthesis that takes into account the placement and routing of the FPGAs.
What is unique about this technology is:
To learn more about this exciting new approach, read more:
I also saw your interview in PCBDesign 007 ... www.pcbdesign007.com/.../zone.cgi ... more good information ... thanks!
I believe we may be able to help you with your challenge. Would you like to connect up with me offline?
My email is email@example.com
We are struggling with high pin count devices and pin/gate swapping and the possibility of tools like this to address the problem. Its not an FPGA, it is a 2k pin count connector set for a semiconductor tester (example - LTX)
I'm wondering if anybody has used a FPGA tool to handle the I/O mapping in an application like this. We have similar I/O rules, like banks of diff pairs, analog channels, power pins etc and we need a way to manage these in a schematic and optimize the routing.
Hi Hemant ... saw the chalk talk “FPGA-PCB Co-design done the right way”
techfocus.acrobat.com/cadence09042801 ... good stuff!