Just a quick blog today on a new 16.5 Allegro PCB Router enhancement for Staggered Via Rules.
The stagger gap value is defined by rules at the following levels:
Option Descriptions:on - turns the rule on.off - turns the rule off (default)min_gap - controls the minimum distance between consecutive vias in the pattern.If min_gap is not specified, a proper samenet bbvia/microvia to samenet bbvia/microvia clearance rule in effect controls the distance. An assigned negative value means no restricted min distance between consecutive vias in the patternmax_gap - controls the maximum distance between consecutive vias in the pattern. If max_gap is not specified (or assigned a negative value) any restrictions exist on max distance between consecutive vias in the pattern.
Examples:#define PCB level rule for staggered bbvias/microvias rule PCB (staggered_via on (min_gap 0.1) (max_gap 0.8))#redefine rule for staggered bbvias/microvias at ‘3_LAYER’rule layer 3_LAYER (staggered_via on (min_gap 0.2) (max_gap 0.7))#redefine rule for staggered bbvias/microvias of nets #from ‘NET_CLASS1’ class rule class NET_CLASS1 (staggered_via on (min_gap 0.3) (max_gap 0.6))#disable PCB level rule (similar rules at different hierarchy #levels are left enabled) rule PCB (staggered_via off)
COST of Via Stagger Violation:
Cost descriptor values are interpreted by the PCB autorouter as follows:- Forbidden, wrong staggered bbvia patterns aren't allowable for building (default)- High, additional cost on wrong staggered bbvia patterns 100- Medium, additional cost on wrong staggered bbvia patterns 25- Low, additional cost on wrong staggered bbvia patterns 8- Free, no additional cost on wrong staggered bbvia patternsNote: At the “converge” stage (either after 5th routing iteration or during “filter” command execution) the autorouter resets this cost to the forbidden value automatically.
I look forward to your input on this capability.
Jerry "GenPart" Grzenia