Beginning with the 16.6 SPB release, FPGA System Planner (FSP) can create net groups automatically whenever an interface is instantiated or a protocol is created. These switches control the auto-creation of those net groups. Turning these on builds the net groups as the design is created:
Read on for more details …The default net group size is 64 signals. Protocols or interfaces with signal groups larger than 64 signals would thus have multiple net groups created. Net groups do not have to be auto-created. Other functionality exists to let you create the net groups later.For interfaces, access to the net groups is via RMB > Configure Connections…RMB on a net group cell opens a pop-up menu:
You can also rename a net group. To place signals in a new net group, select the signals then use Create and Assign New Netgroup:
Selected signals can be manually moved to a different net group. To do this, select the signals, then LMB to get the drop-down on a cell and pick the net group to which you want to move the signal. Remove a signal(s) from a net group by selecting the blank field at the top of the drop-down:
For FPGA protocols the net groups are accessed through the protocol form. The functionality is exactly the same as for interfaces:
A design can be “net grouped” after the fact even if the Settings checkboxes to auto create the net groups are turned off.
Note: Net groups do NOT have to be created in FSP. The design can be forwarded to Allegro with no net groups and the net groups can be created in Allegro and brought back into FSP:
Parts with interface-level constraints must be defined as a single net group.Groups of signals that are constrained in FSP (i.e. “same_bank” or “same_clock_region”) should also be defined as a single net group. The reasons becomes clearer when you get into Allegro and attempt to run the auto pinswap routines. The PCB designer can split the bundles as needed. But, the auto pinswap algorithm doesn’t look simply at the bundle; it looks at the constraints on the signals in the bundle. Thus, the PCB designer cannot arbitrarily create bundles from a group of signals with a “same_clock_region” constraint and expect the tools to let him flowplan those signals anywhere he wants, with no consideration to the other signals. That would violate the FPGA rules.As always – please share your experiences using this new FSP capability!Jerry “GenPart” Grzenia