If you have not yet seen it, Jim Hogan and Paul McLellan wrote
a great piece over at EE Times entitled "The evolution of design methodology"
Their conclusion is that the chip design industry is in the
midst of another major shift to one where chip design becomes software-centric.
In other words, system houses define the end-product, and much of the
differentiation now comes from software. This software lives on across multiple
generations of SoC's. So they are building SoC's so that they run their
software most optimally for the desired system spec (cost, performance, power
consumption, etc). The prototypical example is the A4 chip that Apple designed
to power the iPad. The money quote is "the application drives the hardware."
The article also mentions that in order to design algorithms
that run the software load optimally, "a lot of the algorithms that will be
implemented in silicon (as opposed to running on a microprocessor or digital
signal processor) are written in C or C++ and not RTL."
Given the size and complexity of designing and verifying
these SoC's, there is necessarily a lot of re-use of blocks and subsystems. This
also lends itself to designing in C or C++ and not RTL, since RTL captures the
micro-architecture details associated with the target hardware. As a designer,
you would structure your RTL differently depending on whether performance, power,
or area was the primary concern, and even the target process technology would
influence the RTL.
Jim and Paul have always had a way of distilling complex concepts
into message that are clear to me, and this is no exception. In order to enable
software-centric hardware design, we are going to have to evolve hardware
design from RTL to SystemC. To make that work in the real world, we will need
High-Level Synthesis (HLS) tools that enable entire blocks and subsystems to be
specified in SystemC and synthesized to
RTL that can be implemented through production RTL-GDSII systems and achieve power,
performance, and area that is comparable to hand-crafted RTL.
Over the past few months, I too have been
evolving (my wife says "finally") -- from
RTL synthesis to HLS. I have been working with the C-to-Silicon Compiler team,
and I'm seeing customers achieve the promise of production-worthy HLS (see references below). Now we
need to help support the industry make this large-scale shift. So stay tuned to
and Renesas Enhance Productivity with New System-Level Design Approach
Sets New Productivity Benchmarks with TLM-Drive Design and Verification
A user's first look at
of Cadence C-to-Silicon Compiler Accelerates in Japan