2010 was a very dynamic year for the electronic systems industry overall, and for Cadence in particular. In the next couple of blogs, I would like to focus on some of the trends that started in 2010 and will continue in 2011. In this blog (part I), I will talk about the key growth markets, key industry challenges, and the role of EDA. In the next blog (part II), I will talk about Cadence offerings addressing these challenges.
Key Growth Market -- Application-Driven Internet Mobile
The introduction of Apple's iPad, the continuous success of the Apple's iPhone and the new growth of Google Android based phones propelled the Internet mobile industry in 2010. According to IDC, application-enabled devices will soon overtake PC shipments, reaching 462 million global shipments in 2012 (vs. 448 million PC shipments in the same year).
The drivers for this usage are the content providers and their "apps." Companies such as Facebook (with 500M+ subscribers), movie/video streaming provider Netflix (16M+ subscribers) and the Apple Apps Store (reaching a $1.4B economy and growing at a faster rate than the number of Internet subscribers in 1994-1996) are forcing the system companies (and to some extent the semiconductor companies) to innovate and deliver new products based on new technologies. So definitely, if we look at key growth areas, we should look at mobile Internet, its ecosystem, and expanded industries including the communication infrastructure, cloud computing, gaming and other Internet-based multimedia devices/applications. The EDA360 vision paper published by Cadence in 2010 articulates the market requirements as we migrate to applications-driven devices. This vision paper analyzes the macro trends happening in the electronics industry (including IP, Semiconductor, Software, System and EDA companies) and calls for an action and tight collaboration among the different providers in order to optimize System, SoC and Silicon Realizations.
Key Industry Challenges -- Time-to-volume and Time-to-Integration
In order to address the demands and trends mentioned above, semiconductor and system companies are facing major time-to-market challenges. Their customers (the content providers and their end users) are asking for faster, lower-cost, lower-power mobile Internet devices that can be always-on and work reliably, running a variety of software applications. The software content (in all layers) is exceeding the hardware content, and the end devices are becoming more complex and are requiring multiple processors and many IP blocks. Many devices must provide secured payment transactions and high bandwidth multimedia/video applications through wireless connections, while providing high quality of service.
System design companies are under pressure to change the way they design, verify and integrate. In the past, their focus was on process, back-end optimization, application-specific solutions with differentiation provided through few hardware IP components that were the core for their business. Today, the focus of the system companies is shifting into device optimization for set of software applications and time-to-volume (the ability to ship on time a large volume of devices that will be able to run the applications described above in an optimal and reliable way, at the right cost and power consumption with competitive features). As the development cycle shrinks into 6 months and integration takes 3-4 months, one of the key challenges is the ability to integrate and deliver a new competitive consumer product (including hardware and software) that will hit the market on time.
The EDA role -- More Than a Technology Provider
The EDA industry has a major role solving the key system/SoC challenges mentioned above. As Cadence stated many times within the past year, one company can't do it alone. This should be an industry effort with collaboration of multiple companies. In the last 10 years, the EDA industry initiated a new approach (system-level design, using a higher level of abstraction) in order to solve integration and productivity issues.
During this timeframe, new ESL (Electronic System Level) technologies have been introduced. Some of them were ready to be deployed only recently. Many of the semiconductor companies who ignored these technologies, or had a perception that these technologies are too risky in the past, are now becoming believers and therefore building the infrastructure to deploy them. Others are looking for any new solution that can help them to be more productive. One of these technologies is high-level synthesis, which helps tremendously to increase design and verification productivity through faster IP creation, reuse and faster exploration. When we (Cadence) introduced a new High-Level Synthesis (HLS) product, C-to-Silicon Compiler, to the market 2 years ago, the common questions from the customers were: "What are the potential benefits of HLS? Which standard language is going to evolve? Why should we look into this? How do I know that my Quality of Results (QoR) is going to be at least as good as hand-written RTL?"
By now, SystemC (with C/C++ as a subset) has been accepted as the standard language for high-level design. The key U.S. companies started to acknowledge the value of HLS, and many of the HLS tools are providing good QoR. In 2010, the questions were more along the line of "how can we integrate this technology with our mainstream flow? What do we need to do in order to prepare our infrastructure to use it? How can we educate our engineers so they will be able to use it? Which methodology should we apply?"
I give this as an example to show that EDA providers are becoming more than just technology providers. High-Level Synthesis is just one (albeit important) piece of the puzzle, and it is important for any EDA company to have this technology in order to have key competitive advantages in its portfolio. However, it is as (or more) important for the EDA companies to understand the challenges the IP developers and SoC/system integrators face in order to deploy this technology within their existing flows, and the ecosystem required for deployment.
HLS requires integration with other aspects of the flow such as functional verification and TLM-to-GDS design. It requires a network of service providers or design houses and developers who understand this flow. It requires SystemC education of the previous generation (or next generation). And it requires that hardware engineers have a desire to move to the new flow/methodology.
In my next blog, I will talk about Cadence offerings addressing these challenges. I wish all of you Happy Holidays.