Last year was unprecedented for Cadence. We came up with the EDA360 vision, reorganized
internally to align to that vision, and established some great partnerships to
help our customers realize their own visions around EDA360. The ED360 vision paper
has been well received by both customers and competition, giving further validation
to the concept.
One of the premises of the paper is that
software applications (or "apps") are taking precedence over the hardware.
Applications such as social networking (Facebook), streaming audio (Pandora),
and streaming video (Youtube, Netfix, Hulu ) are driving customers to spend, and
underlying hardware is becoming less relevant (phone, tablet, laptop,
The ideal scenario would be if one could predict
the kind of applications that will become big, and start designing hardware
early, but that is almost impossible given the amount of innovation happening
in the software industry. It would be better if hardware design companies
create hardware at higher levels of abstraction and use automation to implement
the logic as industry trends become more visible.
Cadence understands that this is not a problem
that can be solved by just one EDA company or one design house. The solution
requires EDA companies to work with each other and with customers to create an
ecosystem that will help everyone reduce the design cycle. To foster partnerships, Cadence established the System Realization Alliance program which
offers free licenses and joint marketing opportunities to smaller companies
working in the system realization space on electronic system level (ESL) related technologies.
Last quarter, Cadence offered a platform for all
its System Realization partners to speak to Cadence customers about their
offerings. Nine of our early partners presented webinars to Cadence's customers. The
webinars provided a quick look into tools and services being provided by these
The series started with XtremeEDA. XtremeEDA is
a services organization, based in U.S., that is specializing in verification and ESL
services. They discussed the issues plaguing the ESL market and reasons for
slow adoption of the methodology. The webinar went through new methodologies that
could ease the pain of adopting ESL-based approaches.
The next webinar was presented by CircuitSutra,
which is a specialist services company, focusing on SystemC modeling and virtual prototype development. The webinar showed the power and flexibility of
Virtual Prototypes. Did you know that a virtual prototype can be hooked up to
real world environment by tapping into Ethernet, USB and UART of the host
machine? This opens up a realm of possibilities on the kind of early software
verification you can do.
The third webinar in the series was presented by Imperas.
Imperas is a well known name for all those using or creating virtual prototypes,
because of its impressive line up of fast microcontroller models. Imperas demonstrated
the impressive performance of their models. The throughput of their
models is often higher than real silicon devices. This is a boon for
organizations that want to arm their application development teams with models of hardware well before
hardware is realized.
The fourth was presented by Calypto -- the only
company to have a solution for formal comparison of C/C++/SystemC models with
their RTL implementations. Almost all companies using virtual prototypes use
Calypto's SLEC to keep their silicon implementations synchronized with the virtual prototype throughout the design cycle. Calypto showed off the capabilities of
their SLEC solution. Interestingly, they also showed their power analysis tool
that goes over the RTL and modifies it automatically to reduce the power consumption
without sacrificing functionality or performance.
TSMC reference flow 11 has two aspects covering
the ESL domain. The first is TLM design and verification (TLM D&V) and
the second is High Level Synthesis. We had two webinars presented by TSMC, each
covering one aspect. The TLM design and verification part covers the different
levels of abstraction at which TLM models can be created, how the models at
different levels can interact, and how UVM fits in this scenario. The High Level
Synthesis part covers the ESL methodology that TSMC has established in their
flow to help customers increase productivity by making adoption of HLS easier.
The methodology focuses on creating high-level models in C/C++/SystemC and
using an interactive approach to understand resource and timing requirements of
Cadence Services team has rich experience on
helping our customers adopt ESL solutions. The sixth webinar in the series
covered some case studies of the type of work our services team has done with
customers. Feel free to go through the webinar to see the details.
One of the major roadblocks in adopting virtual prototypes is the availability of TLM models. CoFluent design presented the 8th
webinar in the series and they showed their software CoFluent Studio. This
software lets you capture system specification, either graphically or in Sys-ML,
and generates SystemC TLM code for virtual prototyping.
I have often been asked if functional coverage
on SystemC blocks is possible. The ninth webinar in the series was presented by
JEDA Technologies and they showed their SystemC coverage tool. The nice thing
about their coverage tool is that it performs functional coverage on SystemC
blocks and is hardware aware. Since SystemC code is much smaller (in number of
lines of code) than RTL, you can get relatively high coverage with fewer lines
of testbench code. But same set of tests on RTL would produce much less
coverage. JEDA's coverage tool maps the coverage in SystemC with its possible
coverage in RTL and gives you correct functional coverage upfront.
The final webinar in the series was presented by
Magillem. Magillem provides IP-XACT related software. They have tools to create,
use and check IP-XACT specification for SystemC TLM, RTL or netlist level
blocks. IP-XACT is an IEEE standard that tries to address the issues
encountered when integrating IPs from many sources. With standardized IP-XACT
wrappers, automatic tools can be used to connect IP blocks and generate SoC netlists.
Their webinar showed a demo of their tools and demonstrated the advantages of an IP-XACT driven
flow over a traditional hand assembly flow.
All the webinars have been recorded and archived. Please
visit the link and see the webinars you find interesting. We will resume
the webinar series later in the quarter, and if you want to be made aware of invites for next series, please email me.