It's been an exciting month for the System Realization team with the announcement of our System Development Suite. One of the new products, the Cadence Virtual System Platform, made its debut at the Embedded Systems Conference and has generated a lot of interest from our customers. DAC is right around the corner, and we'll be there with the latest demos of the System Development Suite, and a suite demo focusing on the VIrtual System Platform on Monday at 3pm, Tuesday at 9am, and Wednesday at 4pm. Register online now to reserve a seat for a suite demo.
In parallel to the the Embedded Systems Conference was the CDNLive EMEA user conference in Munich. Cadence offered a tutorial on the System Development Suite that was very well attended. In addition to the demos and roadmap, there was a customer presentation by Ericsson describing their transition to TLM. ARM's Rob Kaye presented about architectural exploration with ARM Fast Models and the Virtual System Platform. Watch for repeats of this presentation at other venues.
Cadence's IP efforts in the SoC Realization organization are also taking advantage of the Virtual System Platform. In this video Sanjay Srivastava, Senior Vice President SoC Realization, discusses the benefits his team derives from using a virtual prototype instead of waiting for FPGA prototypes.
Below is a video demo of the Android SDK running on an ARM-based virtual prototype in the Virtual System Platform. The virtual prototype is connected to the internet through a virtualized Ethernet model, and is accessing actual Internet webpages. It also shows some of the hardware/software debugging capabilities that are needed for hardware-dependent software development.
Part of the Cadence System Development Suite, the Virtual System Platform enables pre-RTL software design, verification, and system analysis before committing to hardware design. It automates the process of creating a virtual prototype, debugging software, and deploying the virtual prototype to the software team—allowing software development to begin months earlier and preventing schedule slips in prototype delivery. The Virtual System Platform also enables transaction-level model (TLM)-aware hardware/software debugging with complete visibility and controllability, and supports mixed TLM/RTL simulation with the Incisive Verification Platform, as well as co-simulation with the Cadence Verification Computing Platform (Palladium XP).
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Mike and Steve: excellent webinar and presentation.
Can you provide more detailed information regarding the interconnect design between the CPU and the external controller used in the initiator driven device?
What about an existing Verilog design that is being ported to a device similar to Android platform. Looks like already working Verilog code would need to be recoded into System-C prior to even getting the testing environment to work.