Code coverage is an effective
tool in the verification process—giving insights into testing completeness as
well as identifying highly active or inactive areas of a design. Collecting
code coverage in simulation on large designs can be a very time consuming
process. Now, code coverage can be collected at emulation speeds in the
Palladium XP system.
Eric Melancon, HSV Staff PE,
explains through his first application note in the series, Accelerating
Code Coverage, that using code
coverage on the Palladium XP system is very analogous to using code coverage in
the Incisive verification environment. This document walks through the
basics of compiling and running designs with code coverage enabled in the
Palladium system. It further answers questions about which types of code coverage can
be accelerated, and how to enable and configure code coverage generation using
further elaborates that the coverage results generated on the Palladium XP
system are collected in the standard Incisive database format. The Palladium UXE software does not provide
any special tools for viewing or analyzing the coverage results. It instead leverages the rich set of tools
and techniques available in the Incisive environment. However, Palladium XP users may not be familiar with those
coverage viewing and analysis tools available in Incisive.
helps us understand the above through
his second app note, Viewing Coverage Data with IMC, by describing how to invoke the IMC tool, how
to load coverage databases generated by UXE, and how to analyze the coverage
results. It is intended to be a simple and quick tour of the basic
functionality available in IMC.
Eric now changes
gears a bit towards functional coverage, which is a verification technique
incorporating design intent into the verification process. This form of
coverage helps us to find answers to functional verification questions like
"Have I exercised all allowed operations?" as well as system performance
questions like "Is my buffer performing optimally?" One vehicle for
incorporating functional coverage into verification is to use the SystemVerilog
covergroup construct. The covergroup construct is supported in the
Palladium XP system. If covergroups were
not supported in accelerated hardware, they would have to be defined and
simulated in an external testbench. This would negatively affect
performance by having to pull signals from the accelerated portion of the
design to the testbench to collect coverage.
this latest app note, How-To Accelerate
SystemVerilog Covergroups, Eric tells us that using SystemVerilog covergroups on the
Palladium XP system is very analogous to using covergroups in the Incisive
verification environment. This app note walks us through the basics of defining,
compiling, and running designs containing covergroups on the Palladium.
Additional how-to documents in
this series will explore methodologies for effectively using accelerated
coverage on the Palladium.
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