Our design is a mix-signal chip. It contains half digital part and half analog part.
In order to have a more accurate system verification, we intend to use Verilog-AMS for the analog model and VHDL as the chip top.
This is the first try for us to do such a verification.
Anyon has idea whether this scheme is applicable or not?
Any reference on similar implementation.
Thanks and Best Regards
it is very much possible to do what you are trying to do. use cadence ams designer for this purpose and its better you use verilog instead of vhdl, or you can use system verilog, systemc as top level module.