i am testing sdram on fpga board. The address , control and data signals for write operation to sdram are going out of the design properly. But, when I am writing to sdram in alternate cycles the data written to higher address locations is being overwritten to lower address locations also.
Like , when i am writing 4 writes each of 16 bit size. The data written to 0001 , 0002 , 0003 location is as expected. But, when i am writing to 0004 location it is being overwritten to 0001 location as well as 0004 location. But, when i am writing with some more delay between consecutive writes, the writes are happening properly. The address, control and data signals going to sdram are as expected and same in both cases. Is it because of routing problem on board. If it is please tell me what exactly the problem might be. I am using Micron 512Mb sdram MT48LC32M16A2. And the writes are done through design ware memory controller IP